1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
4  * Copyright (C) 2012 Renesas Solutions Corp.
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/processor.h>
10 #include <netdev.h>
11 #include <i2c.h>
12 
13 #define MODEMR			(0xFFCC0020)
14 #define MODEMR_MASK		(0x6)
15 #define MODEMR_533MHZ	(0x2)
16 
17 int checkboard(void)
18 {
19 	u32 r = readl(MODEMR);
20 	if ((r & MODEMR_MASK) & MODEMR_533MHZ)
21 		puts("CPU Clock: 533MHz\n");
22 	else
23 		puts("CPU Clock: 400MHz\n");
24 
25 	puts("BOARD: Alpha Project. AP-SH4A-4A\n");
26 	return 0;
27 }
28 
29 #define MSTPSR1			(0xFFC80044)
30 #define MSTPCR1			(0xFFC80034)
31 #define MSTPSR1_GETHER	(1 << 14)
32 
33 /* IPSR3 */
34 #define ET0_ETXD0 (0x4 << 3)
35 #define ET0_GTX_CLK_A (0x4 << 6)
36 #define ET0_ETXD1_A (0x4 << 9)
37 #define ET0_ETXD2_A (0x4 << 12)
38 #define ET0_ETXD3_A (0x4 << 15)
39 #define ET0_ETXD4 (0x3 << 18)
40 #define ET0_ETXD5_A (0x5 << 21)
41 #define ET0_ETXD6_A (0x5 << 24)
42 #define ET0_ETXD7 (0x4 << 27)
43 #define IPSR3_ETH_ENABLE \
44 	(ET0_ETXD0 | ET0_GTX_CLK_A | ET0_ETXD1_A | ET0_ETXD2_A | \
45 	ET0_ETXD3_A | ET0_ETXD4 | ET0_ETXD5_A | ET0_ETXD6_A | ET0_ETXD7)
46 
47 /* IPSR4 */
48 #define ET0_ERXD7	(0x4)
49 #define ET0_RX_DV	(0x4 << 3)
50 #define ET0_RX_ER	(0x4 << 6)
51 #define ET0_CRS		(0x4 << 9)
52 #define ET0_COL		(0x4 << 12)
53 #define ET0_MDC		(0x4 << 15)
54 #define ET0_MDIO_A	(0x3 << 18)
55 #define ET0_LINK_A	(0x3 << 20)
56 #define ET0_PHY_INT_A (0x3 << 24)
57 
58 #define IPSR4_ETH_ENABLE \
59 	(ET0_ERXD7 | ET0_RX_DV | ET0_RX_ER | ET0_CRS | ET0_COL | \
60 	ET0_MDC | ET0_MDIO_A | ET0_LINK_A | ET0_PHY_INT_A)
61 
62 /* IPSR8 */
63 #define ET0_ERXD0	(0x4 << 20)
64 #define ET0_ERXD1	(0x4 << 23)
65 #define ET0_ERXD2_A (0x3 << 26)
66 #define ET0_ERXD3_A (0x3 << 28)
67 #define IPSR8_ETH_ENABLE \
68 	(ET0_ERXD0 | ET0_ERXD1 | ET0_ERXD2_A | ET0_ERXD3_A)
69 
70 /* IPSR10 */
71 #define RX4_D	(0x1 << 22)
72 #define TX4_D	(0x1 << 23)
73 #define IPSR10_SCIF_ENABLE (RX4_D | TX4_D)
74 
75 /* IPSR11 */
76 #define ET0_ERXD4	(0x4 <<  4)
77 #define ET0_ERXD5	(0x4 <<  7)
78 #define ET0_ERXD6	(0x3 << 10)
79 #define ET0_TX_EN	(0x2 << 19)
80 #define ET0_TX_ER	(0x2 << 21)
81 #define ET0_TX_CLK_A (0x4 << 23)
82 #define ET0_RX_CLK_A (0x3 << 26)
83 #define IPSR11_ETH_ENABLE \
84 	(ET0_ERXD4 | ET0_ERXD5 | ET0_ERXD6 | ET0_TX_EN | ET0_TX_ER | \
85 	ET0_TX_CLK_A | ET0_RX_CLK_A)
86 
87 #define GPSR1_INIT (0xFFFF7FFF)
88 #define GPSR2_INIT (0x4005FEFF)
89 #define GPSR3_INIT (0x2EFFFFFF)
90 #define GPSR4_INIT (0xC7000000)
91 
92 int board_init(void)
93 {
94 	u32 data;
95 
96 	/* Set IPSR register */
97 	data = readl(IPSR3);
98 	data |= IPSR3_ETH_ENABLE;
99 	writel(~data, PMMR);
100 	writel(data, IPSR3);
101 
102 	data = readl(IPSR4);
103 	data |= IPSR4_ETH_ENABLE;
104 	writel(~data, PMMR);
105 	writel(data, IPSR4);
106 
107 	data = readl(IPSR8);
108 	data |= IPSR8_ETH_ENABLE;
109 	writel(~data, PMMR);
110 	writel(data, IPSR8);
111 
112 	data = readl(IPSR10);
113 	data |= IPSR10_SCIF_ENABLE;
114 	writel(~data, PMMR);
115 	writel(data, IPSR10);
116 
117 	data = readl(IPSR11);
118 	data |= IPSR11_ETH_ENABLE;
119 	writel(~data, PMMR);
120 	writel(data, IPSR11);
121 
122 	/* GPIO select */
123 	data = GPSR1_INIT;
124 	writel(~data, PMMR);
125 	writel(data, GPSR1);
126 
127 	data = GPSR2_INIT;
128 	writel(~data, PMMR);
129 	writel(data, GPSR2);
130 
131 	data = GPSR3_INIT;
132 	writel(~data, PMMR);
133 	writel(data, GPSR3);
134 
135 	data = GPSR4_INIT;
136 	writel(~data, PMMR);
137 	writel(data, GPSR4);
138 
139 	data = 0x0;
140 	writel(~data, PMMR);
141 	writel(data, GPSR5);
142 
143 	/* mode select */
144 	data = MODESEL2_INIT;
145 	writel(~data, PMMR);
146 	writel(data, MODESEL2);
147 
148 #if defined(CONFIG_SH_ETHER)
149 	u32 r = readl(MSTPSR1);
150 	if (r & MSTPSR1_GETHER)
151 		writel((r & ~MSTPSR1_GETHER), MSTPCR1);
152 #endif
153 	return 0;
154 }
155 
156 int board_late_init(void)
157 {
158 	printf("Cannot use I2C to get MAC address\n");
159 
160 	return 0;
161 }
162