1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017 Allied Telesis Labs 4 */ 5 6 #include <common.h> 7 #include <command.h> 8 #include <dm.h> 9 #include <i2c.h> 10 #include <asm/gpio.h> 11 #include <linux/mbus.h> 12 #include <linux/io.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/arch/soc.h> 15 #include "../common/gpio_hog.h" 16 17 #include "../drivers/ddr/marvell/a38x/ddr3_init.h" 18 #include <../serdes/a38x/high_speed_env_spec.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400)) 23 24 #define CONFIG_NVS_LOCATION 0xf4800000 25 #define CONFIG_NVS_SIZE (512 << 10) 26 27 static struct serdes_map board_serdes_map[] = { 28 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 29 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 30 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 31 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 32 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 33 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0} 34 }; 35 36 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) 37 { 38 *serdes_map_array = board_serdes_map; 39 *count = ARRAY_SIZE(board_serdes_map); 40 return 0; 41 } 42 43 /* 44 * Define the DDR layout / topology here in the board file. This will 45 * be used by the DDR3 init code in the SPL U-Boot version to configure 46 * the DDR3 controller. 47 */ 48 static struct mv_ddr_topology_map board_topology_map = { 49 DEBUG_LEVEL_ERROR, 50 0x1, /* active interfaces */ 51 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ 52 { { { {0x1, 0, 0, 0}, 53 {0x1, 0, 0, 0}, 54 {0x1, 0, 0, 0}, 55 {0x1, 0, 0, 0}, 56 {0x1, 0, 0, 0} }, 57 SPEED_BIN_DDR_1866M, /* speed_bin */ 58 MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */ 59 MV_DDR_DIE_CAP_4GBIT, /* die capacity */ 60 MV_DDR_FREQ_SAR, /* frequency */ 61 0, 0, /* cas_l cas_wl */ 62 MV_DDR_TEMP_LOW, /* temperature */ 63 MV_DDR_TIM_2T} }, /* timing */ 64 BUS_MASK_32BIT_ECC, /* subphys mask */ 65 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ 66 { {0} }, /* raw spd data */ 67 {0} /* timing parameters */ 68 }; 69 70 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) 71 { 72 /* Return the board topology as defined in the board code */ 73 return &board_topology_map; 74 } 75 76 int board_early_init_f(void) 77 { 78 /* Configure MPP */ 79 writel(0x00001111, MVEBU_MPP_BASE + 0x00); 80 writel(0x00000000, MVEBU_MPP_BASE + 0x04); 81 writel(0x55000000, MVEBU_MPP_BASE + 0x08); 82 writel(0x55550550, MVEBU_MPP_BASE + 0x0c); 83 writel(0x55555555, MVEBU_MPP_BASE + 0x10); 84 writel(0x00100565, MVEBU_MPP_BASE + 0x14); 85 writel(0x40000000, MVEBU_MPP_BASE + 0x18); 86 writel(0x00004444, MVEBU_MPP_BASE + 0x1c); 87 88 return 0; 89 } 90 91 int board_init(void) 92 { 93 /* address of boot parameters */ 94 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 95 96 /* window for NVS */ 97 mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE, 98 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1); 99 100 /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */ 101 writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8); 102 103 return 0; 104 } 105 106 static int led_7seg_init(unsigned int segments) 107 { 108 int node; 109 int ret; 110 int i; 111 struct gpio_desc desc[8]; 112 113 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, 114 "atl,of-led-7seg"); 115 if (node < 0) 116 return -ENODEV; 117 118 ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node), 119 "segment-gpios", desc, 120 ARRAY_SIZE(desc), GPIOD_IS_OUT); 121 if (ret < 0) 122 return ret; 123 124 for (i = 0; i < ARRAY_SIZE(desc); i++) { 125 ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i))); 126 if (ret) 127 return ret; 128 } 129 130 return 0; 131 } 132 133 #ifdef CONFIG_MISC_INIT_R 134 int misc_init_r(void) 135 { 136 static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {}, 137 led_en = {}; 138 139 gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1); 140 gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1); 141 gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0); 142 gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1); 143 144 #ifdef MTDPARTS_MTDOOPS 145 env_set("mtdoops", MTDPARTS_MTDOOPS); 146 #endif 147 148 led_7seg_init(0xff); 149 150 return 0; 151 } 152 #endif 153 154 #ifdef CONFIG_DISPLAY_BOARDINFO 155 int checkboard(void) 156 { 157 puts("Board: " CONFIG_SYS_BOARD "\n"); 158 159 return 0; 160 } 161 #endif 162