1/* set the default clock gate to save power */
2DATA 4, CCM_CCGR0, 0x00C03F3F
3DATA 4, CCM_CCGR1, 0x0030FC03
4DATA 4, CCM_CCGR2, 0x0FFFC000
5DATA 4, CCM_CCGR3, 0x3FF00000
6DATA 4, CCM_CCGR4, 0x00FFF300
7DATA 4, CCM_CCGR5, 0x0F0000C3
8DATA 4, CCM_CCGR6, 0x000003FF
9
10/* enable AXI cache for VDOA/VPU/IPU */
11DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
12/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
13DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
14DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
15
16/*
17 * Setup CCM_CCOSR register as follows:
18 *
19 * cko1_en  1    --> CKO1 enabled
20 * cko1_div 111  --> divide by 8
21 * cko1_sel 1011 --> ahb_clk_root
22 *
23 * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
24 */
25DATA 4, CCM_CCOSR, 0x000000fb
26