1# 2# (C) Copyright 2011 3# Jason Cooper <u-boot@lakedaemon.net> 4# 5# Based on work by: 6# Marvell Semiconductor <www.marvell.com> 7# Written-by: Siddarth Gore <gores@marvell.com> 8# 9# SPDX-License-Identifier: GPL-2.0+ 10# 11# Refer doc/README.kwbimage for more details about how-to configure 12# and create kirkwood boot image 13# 14 15# Boot Media configurations 16BOOT_FROM spi 17 18# SOC registers configuration using bootrom header extension 19# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 20 21# Configure RGMII-0/1 interface pad voltage to 1.8V 22DATA 0xFFD100e0 0x1b1b1b9b 23 24DATA 0xFFD20134 0xbbbbbbbb 25DATA 0xFFD20138 0x00bbbbbb 26 27#Dram initalization for SINGLE x16 CL=5 @ 400MHz 28DATA 0xFFD01400 0x43000c30 # DDR Configuration register 29# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 30# bit23-14: zero 31# bit24: 1= enable exit self refresh mode on DDR access 32# bit25: 1 required 33# bit29-26: zero 34# bit31-30: 01 35 36DATA 0xFFD01404 0x39543000 # DDR Controller Control Low 37# bit 4: 0=addr/cmd in smame cycle 38# bit 5: 0=clk is driven during self refresh, we don't care for APX 39# bit 6: 0=use recommended falling edge of clk for addr/cmd 40# bit14: 0=input buffer always powered up 41# bit18: 1=cpu lock transaction enabled 42# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 43# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 44# bit30-28: 3 required 45# bit31: 0=no additional STARTBURST delay 46 47DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) 48# bit3-0: TRAS lsbs 49# bit7-4: TRCD 50# bit11- 8: TRP 51# bit15-12: TWR 52# bit19-16: TWTR 53# bit20: TRAS msb 54# bit23-21: 0x0 55# bit27-24: TRRD 56# bit31-28: TRTP 57 58DATA 0xFFD0140C 0x00000833 # DDR Timing (High) 59# bit6-0: TRFC 60# bit8-7: TR2R 61# bit10-9: TR2W 62# bit12-11: TW2W 63# bit31-13: zero required 64 65DATA 0xFFD01410 0x0000000d # DDR Address Control 66# bit1-0: 01, Cs0width=x8 67# bit3-2: 10, Cs0size=1Gb 68# bit5-4: 01, Cs1width=x8 69# bit7-6: 10, Cs1size=1Gb 70# bit9-8: 00, Cs2width=nonexistent 71# bit11-10: 00, Cs2size =nonexistent 72# bit13-12: 00, Cs3width=nonexistent 73# bit15-14: 00, Cs3size =nonexistent 74# bit16: 0, Cs0AddrSel 75# bit17: 0, Cs1AddrSel 76# bit18: 0, Cs2AddrSel 77# bit19: 0, Cs3AddrSel 78# bit31-20: 0 required 79 80DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 81# bit0: 0, OpenPage enabled 82# bit31-1: 0 required 83 84DATA 0xFFD01418 0x00000000 # DDR Operation 85# bit3-0: 0x0, DDR cmd 86# bit31-4: 0 required 87 88DATA 0xFFD0141C 0x00000C52 # DDR Mode 89# bit2-0: 2, BurstLen=2 required 90# bit3: 0, BurstType=0 required 91# bit6-4: 4, CL=5 92# bit7: 0, TestMode=0 normal 93# bit8: 0, DLL reset=0 normal 94# bit11-9: 6, auto-precharge write recovery ???????????? 95# bit12: 0, PD must be zero 96# bit31-13: 0 required 97 98DATA 0xFFD01420 0x00000042 # DDR Extended Mode 99# bit0: 0, DDR DLL enabled 100# bit1: 0, DDR drive strenght normal 101# bit2: 0, DDR ODT control lsd (disabled) 102# bit5-3: 000, required 103# bit6: 1, DDR ODT control msb, (disabled) 104# bit9-7: 000, required 105# bit10: 0, differential DQS enabled 106# bit11: 0, required 107# bit12: 0, DDR output buffer enabled 108# bit31-13: 0 required 109 110DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High 111# bit2-0: 111, required 112# bit3 : 1 , MBUS Burst Chop disabled 113# bit6-4: 111, required 114# bit7 : 0 115# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz 116# bit9 : 0 , no half clock cycle addition to dataout 117# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 118# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 119# bit15-12: 1111 required 120# bit31-16: 0 required 121 122DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) 123DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) 124 125DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 126DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size 127# bit0: 1, Window enabled 128# bit1: 0, Write Protect disabled 129# bit3-2: 00, CS0 hit selected 130# bit23-4: ones, required 131# bit31-24: 0x07, Size (i.e. 128MB) 132 133DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb 134DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 135 136DATA 0xFFD01510 0x20000000 # CS[2]n Base address to 256Mb 137DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 138DATA 0xFFD01518 0x30000000 # CS[3]n Base address to 256Mb 139DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 140 141DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low) 142DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 143# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 144# bit3-2: 01, ODT1 active NEVER! 145# bit31-4: zero, required 146 147DATA 0xFFD0149C 0x0000F80F # CPU ODT Control 148DATA 0xFFD01480 0x00000001 # DDR Initialization Control 149#bit0=1, enable DDR init upon this register write 150 151# End of Header extension 152DATA 0x0 0x0 153