xref: /openbmc/u-boot/board/Seagate/nas220/nas220.c (revision a373024e)
1 /*
2  * Copyright (C) 2014  Evgeni Dobrev <evgeni@studio-punkt.com>
3  *
4  * Based on sheevaplug.c originally written by
5  * Prafulla Wadaskar <prafulla@marvell.com>
6  * (C) Copyright 2009
7  * Marvell Semiconductor <www.marvell.com>
8  *
9  * SPDX-License-Identifier:     GPL-2.0+
10  */
11 
12 #include <common.h>
13 #include <miiphy.h>
14 #include <asm/mach-types.h>
15 #include <asm/arch/soc.h>
16 #include <asm/arch/mpp.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/io.h>
19 
20 DECLARE_GLOBAL_DATA_PTR;
21 
22 int board_early_init_f(void)
23 {
24 	/*
25 	 * default gpio configuration
26 	 */
27 	mvebu_config_gpio(NAS220_GE_OE_VAL_LOW, NAS220_GE_OE_VAL_HIGH,
28 			  NAS220_GE_OE_LOW, NAS220_GE_OE_HIGH);
29 
30 	/* Multi-Purpose Pins Functionality configuration */
31 	static const u32 kwmpp_config[] = {
32 		MPP0_NF_IO2,
33 		MPP1_NF_IO3,
34 		MPP2_NF_IO4,
35 		MPP3_NF_IO5,
36 		MPP4_NF_IO6,
37 		MPP5_NF_IO7,
38 		MPP6_SYSRST_OUTn,
39 		MPP7_SPI_SCn,
40 		MPP8_TW_SDA,
41 		MPP9_TW_SCK,
42 		MPP10_UART0_TXD,
43 		MPP11_UART0_RXD,
44 		MPP12_GPO,
45 		MPP13_GPIO,
46 		MPP14_GPIO,
47 		MPP15_SATA0_ACTn,
48 		MPP16_SATA1_ACTn,
49 		MPP17_SATA0_PRESENTn,
50 		MPP18_NF_IO0,
51 		MPP19_NF_IO1,
52 		MPP20_GPIO,
53 		MPP21_GPIO,
54 		MPP22_GPIO,
55 		MPP23_GPIO,
56 		MPP24_GPIO,
57 		MPP25_GPIO,
58 		MPP26_GPIO,
59 		MPP27_GPIO,
60 		MPP28_GPIO,
61 		MPP29_GPIO,
62 		MPP30_GPIO,
63 		MPP31_GPIO,
64 		MPP32_GPIO,
65 		MPP33_GPIO,
66 		MPP34_GPIO,
67 		MPP35_GPIO,
68 		0
69 	};
70 	kirkwood_mpp_conf(kwmpp_config, NULL);
71 	return 0;
72 }
73 
74 int board_init(void)
75 {
76 	/*
77 	 * arch number of board
78 	 */
79 	gd->bd->bi_arch_number = MACH_TYPE_RD88F6192_NAS;
80 
81 	/* adress of boot parameters */
82 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
83 
84 	return 0;
85 }
86 
87 #ifdef CONFIG_RESET_PHY_R
88 /* Configure and enable MV88E1116 PHY */
89 void reset_phy(void)
90 {
91 	u16 reg;
92 	u16 devadr;
93 	char *name = "egiga0";
94 
95 	if (miiphy_set_current_dev(name))
96 		return;
97 
98 	/* command to read PHY dev address */
99 	if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
100 		printf("Err..%s could not read PHY dev address\n", __func__);
101 		return;
102 	}
103 
104 	/*
105 	 * Enable RGMII delay on Tx and Rx for CPU port
106 	 * Ref: sec 4.7.2 of chip datasheet
107 	 */
108 	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
109 	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
110 	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
111 	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
112 	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
113 
114 	/* reset the phy */
115 	miiphy_reset(name, devadr);
116 
117 	printf("88E1116 Initialized on %s\n", name);
118 }
119 #endif /* CONFIG_RESET_PHY_R */
120