1# 2# Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com> 3# 4# Based on sheevaplug/kwbimage.cfg originally written by 5# Prafulla Wadaskar <prafulla@marvell.com> 6# (C) Copyright 2009 7# Marvell Semiconductor <www.marvell.com> 8# 9# SPDX-License-Identifier: GPL-2.0+ 10# 11# Refer doc/README.kwbimage for more details about how-to configure 12# and create kirkwood boot image 13# 14 15# Boot Media configurations 16BOOT_FROM nand 17NAND_ECC_MODE default 18NAND_PAGE_SIZE 0x0200 19 20# SOC registers configuration using bootrom header extension 21# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 22 23# Configure RGMII-0 interface pad voltage to 1.8V 24DATA 0xFFD100e0 0x1b1b1b9b 25 26#Dram initalization for SINGLE x16 CL=5 @ 400MHz 27DATA 0xFFD01400 0x43000618 # DDR Configuration register 28# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) 29# bit23-14: zero 30# bit24: 1= enable exit self refresh mode on DDR access 31# bit25: 1 required 32# bit29-26: zero 33# bit31-30: 01 34 35DATA 0xFFD01404 0x35143000 # DDR Controller Control Low 36# bit 4: 0=addr/cmd in smame cycle 37# bit 5: 0=clk is driven during self refresh, we don't care for APX 38# bit 6: 0=use recommended falling edge of clk for addr/cmd 39# bit14: 0=input buffer always powered up 40# bit18: 1=cpu lock transaction enabled 41# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 42# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 43# bit30-28: 3 required 44# bit31: 0=no additional STARTBURST delay 45 46DATA 0xFFD01408 0x11012227 # DDR Timing (Low) (active cycles value +1) 47# bit7-4: TRCD 48# bit11- 8: TRP 49# bit15-12: TWR 50# bit19-16: TWTR 51# bit20: TRAS msb 52# bit23-21: 0x0 53# bit27-24: TRRD 54# bit31-28: TRTP 55 56DATA 0xFFD0140C 0x00000819 # DDR Timing (High) 57# bit6-0: TRFC 58# bit8-7: TR2R 59# bit10-9: TR2W 60# bit12-11: TW2W 61# bit31-13: zero required 62 63 64DATA 0xFFD01410 0x0000000d # DDR Address Control 65# bit1-0: 00, Cs0width=x8 66# bit3-2: 11, Cs0size=1Gb 67# bit5-4: 00, Cs1width=nonexistent 68# bit7-6: 00, Cs1size =nonexistent 69# bit9-8: 00, Cs2width=nonexistent 70# bit11-10: 00, Cs2size =nonexistent 71# bit13-12: 00, Cs3width=nonexistent 72# bit15-14: 00, Cs3size =nonexistent 73# bit16: 0, Cs0AddrSel 74# bit17: 0, Cs1AddrSel 75# bit18: 0, Cs2AddrSel 76# bit19: 0, Cs3AddrSel 77# bit31-20: 0 required 78 79DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 80# bit0: 0, OpenPage enabled 81# bit31-1: 0 required 82 83DATA 0xFFD01418 0x00000000 # DDR Operation 84# bit3-0: 0x0, DDR cmd 85# bit31-4: 0 required 86 87DATA 0xFFD0141C 0x00000632 # DDR Mode 88# bit2-0: 2, BurstLen=2 required 89# bit3: 0, BurstType=0 required 90# bit6-4: 4, CL=5 91# bit7: 0, TestMode=0 normal 92# bit8: 0, DLL reset=0 normal 93# bit11-9: 6, auto-precharge write recovery ???????????? 94# bit12: 0, PD must be zero 95# bit31-13: 0 required 96 97 98DATA 0xFFD01420 0x00000040 # DDR Extended Mode 99# bit0: 0, DDR DLL enabled 100# bit1: 0, DDR drive strenght normal 101# bit2: 0, DDR ODT control lsd (disabled) 102# bit5-3: 000, required 103# bit6: 1, DDR ODT control msb, (disabled) 104# bit9-7: 000, required 105# bit10: 0, differential DQS enabled 106# bit11: 0, required 107# bit12: 0, DDR output buffer enabled 108# bit31-13: 0 required 109 110DATA 0xFFD01424 0x0000F07F # DDR Controller Control High 111# bit2-0: 111, required 112# bit3 : 1 , MBUS Burst Chop disabled 113# bit6-4: 111, required 114# bit7 : 0 115# bit8 : 0 116# bit9 : 0 , no half clock cycle addition to dataout 117# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 118# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 119# bit15-12: 1111 required 120# bit31-16: 0 required 121 122DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size 123# bit0: 1, Window enabled 124# bit1: 0, Write Protect disabled 125# bit3-2: 00, CS0 hit selected 126# bit23-4: ones, required 127# bit31-24: 0x07, Size (i.e. 128MB) 128 129DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 130 131DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 132 133DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 134DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 135 136DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) 137DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 138# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 139# bit3-2: 01, ODT1 active NEVER! 140# bit31-4: zero, required 141 142DATA 0xFFD0149C 0x0000E803 # CPU ODT Control 143 144DATA 0xFFD01480 0x00000001 # DDR Initialization Control 145#bit0=1, enable DDR init upon this register write 146 147DATA 0xffd01620 0x00465000 148 149# End of Header extension 150DATA 0x0 0x0 151 152