1# 2# Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com> 3# 4# Based on dockstar/kwbimage.cfg originally written by 5# Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu> 6# 7# Based on sheevaplug/kwbimage.cfg originally written by 8# Prafulla Wadaskar <prafulla@marvell.com> 9# (C) Copyright 2009 10# Marvell Semiconductor <www.marvell.com> 11# 12# See file CREDITS for list of people who contributed to this 13# project. 14# 15# This program is free software; you can redistribute it and/or 16# modify it under the terms of the GNU General Public License as 17# published by the Free Software Foundation; either version 2 of 18# the License, or (at your option) any later version. 19# 20# This program is distributed in the hope that it will be useful, 21# but WITHOUT ANY WARRANTY; without even the implied warranty of 22# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23# GNU General Public License for more details. 24# 25# You should have received a copy of the GNU General Public License 26# along with this program; if not, write to the Free Software 27# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 28# MA 02110-1301 USA 29# 30# Refer docs/README.kwimage for more details about how-to configure 31# and create kirkwood boot image 32# 33 34# Boot Media configurations 35BOOT_FROM nand 36NAND_ECC_MODE default 37NAND_PAGE_SIZE 0x0800 38 39# SOC registers configuration using bootrom header extension 40# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 41 42# Configure RGMII-0 interface pad voltage to 1.8V 43DATA 0xFFD100e0 0x1b1b1b9b 44 45#Dram initalization for SINGLE x16 CL=5 @ 400MHz 46DATA 0xFFD01400 0x43000c30 # DDR Configuration register 47# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 48# bit23-14: zero 49# bit24: 1= enable exit self refresh mode on DDR access 50# bit25: 1 required 51# bit29-26: zero 52# bit31-30: 01 53 54DATA 0xFFD01404 0x37543000 # DDR Controller Control Low 55# bit 4: 0=addr/cmd in smame cycle 56# bit 5: 0=clk is driven during self refresh, we don't care for APX 57# bit 6: 0=use recommended falling edge of clk for addr/cmd 58# bit14: 0=input buffer always powered up 59# bit18: 1=cpu lock transaction enabled 60# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 61# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 62# bit30-28: 3 required 63# bit31: 0=no additional STARTBURST delay 64 65DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) 66# bit3-0: TRAS lsbs 67# bit7-4: TRCD 68# bit11- 8: TRP 69# bit15-12: TWR 70# bit19-16: TWTR 71# bit20: TRAS msb 72# bit23-21: 0x0 73# bit27-24: TRRD 74# bit31-28: TRTP 75 76DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) 77# bit6-0: TRFC 78# bit8-7: TR2R 79# bit10-9: TR2W 80# bit12-11: TW2W 81# bit31-13: zero required 82 83DATA 0xFFD01410 0x0000000d # DDR Address Control 84# bit1-0: 00, Cs0width=x8 85# bit3-2: 11, Cs0size=1Gb 86# bit5-4: 00, Cs1width=nonexistent 87# bit7-6: 00, Cs1size =nonexistent 88# bit9-8: 00, Cs2width=nonexistent 89# bit11-10: 00, Cs2size =nonexistent 90# bit13-12: 00, Cs3width=nonexistent 91# bit15-14: 00, Cs3size =nonexistent 92# bit16: 0, Cs0AddrSel 93# bit17: 0, Cs1AddrSel 94# bit18: 0, Cs2AddrSel 95# bit19: 0, Cs3AddrSel 96# bit31-20: 0 required 97 98DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 99# bit0: 0, OpenPage enabled 100# bit31-1: 0 required 101 102DATA 0xFFD01418 0x00000000 # DDR Operation 103# bit3-0: 0x0, DDR cmd 104# bit31-4: 0 required 105 106DATA 0xFFD0141C 0x00000C52 # DDR Mode 107# bit2-0: 2, BurstLen=2 required 108# bit3: 0, BurstType=0 required 109# bit6-4: 4, CL=5 110# bit7: 0, TestMode=0 normal 111# bit8: 0, DLL reset=0 normal 112# bit11-9: 6, auto-precharge write recovery ???????????? 113# bit12: 0, PD must be zero 114# bit31-13: 0 required 115 116DATA 0xFFD01420 0x00000040 # DDR Extended Mode 117# bit0: 0, DDR DLL enabled 118# bit1: 0, DDR drive strenght normal 119# bit2: 0, DDR ODT control lsd (disabled) 120# bit5-3: 000, required 121# bit6: 1, DDR ODT control msb, (disabled) 122# bit9-7: 000, required 123# bit10: 0, differential DQS enabled 124# bit11: 0, required 125# bit12: 0, DDR output buffer enabled 126# bit31-13: 0 required 127 128DATA 0xFFD01424 0x0000F17F # DDR Controller Control High 129# bit2-0: 111, required 130# bit3 : 1 , MBUS Burst Chop disabled 131# bit6-4: 111, required 132# bit7 : 0 133# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz 134# bit9 : 0 , no half clock cycle addition to dataout 135# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 136# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 137# bit15-12: 1111 required 138# bit31-16: 0 required 139 140DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) 141DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) 142 143DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 144DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size 145# bit0: 1, Window enabled 146# bit1: 0, Write Protect disabled 147# bit3-2: 00, CS0 hit selected 148# bit23-4: ones, required 149# bit31-24: 0x07, Size (i.e. 128MB) 150 151DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb 152DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 153 154DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 155DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 156 157DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) 158DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 159# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 160# bit3-2: 01, ODT1 active NEVER! 161# bit31-4: zero, required 162 163DATA 0xFFD0149C 0x0000E803 # CPU ODT Control 164DATA 0xFFD01480 0x00000001 # DDR Initialization Control 165#bit0=1, enable DDR init upon this register write 166 167# End of Header extension 168DATA 0x0 0x0 169