1# 2# Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu> 3# 4# Based on sheevaplug/kwbimage.cfg originally written by 5# Prafulla Wadaskar <prafulla@marvell.com> 6# (C) Copyright 2009 7# Marvell Semiconductor <www.marvell.com> 8# 9# See file CREDITS for list of people who contributed to this 10# project. 11# 12# This program is free software; you can redistribute it and/or 13# modify it under the terms of the GNU General Public License as 14# published by the Free Software Foundation; either version 2 of 15# the License, or (at your option) any later version. 16# 17# This program is distributed in the hope that it will be useful, 18# but WITHOUT ANY WARRANTY; without even the implied warranty of 19# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20# GNU General Public License for more details. 21# 22# You should have received a copy of the GNU General Public License 23# along with this program; if not, write to the Free Software 24# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 25# MA 02110-1301 USA 26# 27# Refer doc/README.kwbimage for more details about how-to configure 28# and create kirkwood boot image 29# 30 31# Boot Media configurations 32BOOT_FROM nand 33NAND_ECC_MODE default 34NAND_PAGE_SIZE 0x0800 35 36# SOC registers configuration using bootrom header extension 37# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 38 39# Configure RGMII-0 interface pad voltage to 1.8V 40DATA 0xFFD100e0 0x1b1b1b9b 41 42#Dram initalization for SINGLE x16 CL=5 @ 400MHz 43DATA 0xFFD01400 0x43000c30 # DDR Configuration register 44# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 45# bit23-14: zero 46# bit24: 1= enable exit self refresh mode on DDR access 47# bit25: 1 required 48# bit29-26: zero 49# bit31-30: 01 50 51DATA 0xFFD01404 0x37543000 # DDR Controller Control Low 52# bit 4: 0=addr/cmd in smame cycle 53# bit 5: 0=clk is driven during self refresh, we don't care for APX 54# bit 6: 0=use recommended falling edge of clk for addr/cmd 55# bit14: 0=input buffer always powered up 56# bit18: 1=cpu lock transaction enabled 57# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 58# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 59# bit30-28: 3 required 60# bit31: 0=no additional STARTBURST delay 61 62DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) 63# bit3-0: TRAS lsbs 64# bit7-4: TRCD 65# bit11- 8: TRP 66# bit15-12: TWR 67# bit19-16: TWTR 68# bit20: TRAS msb 69# bit23-21: 0x0 70# bit27-24: TRRD 71# bit31-28: TRTP 72 73DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) 74# bit6-0: TRFC 75# bit8-7: TR2R 76# bit10-9: TR2W 77# bit12-11: TW2W 78# bit31-13: zero required 79 80DATA 0xFFD01410 0x0000000d # DDR Address Control 81# bit1-0: 00, Cs0width=x8 82# bit3-2: 11, Cs0size=1Gb 83# bit5-4: 00, Cs1width=nonexistent 84# bit7-6: 00, Cs1size =nonexistent 85# bit9-8: 00, Cs2width=nonexistent 86# bit11-10: 00, Cs2size =nonexistent 87# bit13-12: 00, Cs3width=nonexistent 88# bit15-14: 00, Cs3size =nonexistent 89# bit16: 0, Cs0AddrSel 90# bit17: 0, Cs1AddrSel 91# bit18: 0, Cs2AddrSel 92# bit19: 0, Cs3AddrSel 93# bit31-20: 0 required 94 95DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 96# bit0: 0, OpenPage enabled 97# bit31-1: 0 required 98 99DATA 0xFFD01418 0x00000000 # DDR Operation 100# bit3-0: 0x0, DDR cmd 101# bit31-4: 0 required 102 103DATA 0xFFD0141C 0x00000C52 # DDR Mode 104# bit2-0: 2, BurstLen=2 required 105# bit3: 0, BurstType=0 required 106# bit6-4: 4, CL=5 107# bit7: 0, TestMode=0 normal 108# bit8: 0, DLL reset=0 normal 109# bit11-9: 6, auto-precharge write recovery ???????????? 110# bit12: 0, PD must be zero 111# bit31-13: 0 required 112 113DATA 0xFFD01420 0x00000040 # DDR Extended Mode 114# bit0: 0, DDR DLL enabled 115# bit1: 0, DDR drive strenght normal 116# bit2: 0, DDR ODT control lsd (disabled) 117# bit5-3: 000, required 118# bit6: 1, DDR ODT control msb, (disabled) 119# bit9-7: 000, required 120# bit10: 0, differential DQS enabled 121# bit11: 0, required 122# bit12: 0, DDR output buffer enabled 123# bit31-13: 0 required 124 125DATA 0xFFD01424 0x0000F17F # DDR Controller Control High 126# bit2-0: 111, required 127# bit3 : 1 , MBUS Burst Chop disabled 128# bit6-4: 111, required 129# bit7 : 0 130# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz 131# bit9 : 0 , no half clock cycle addition to dataout 132# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 133# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 134# bit15-12: 1111 required 135# bit31-16: 0 required 136 137DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) 138DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) 139 140DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 141DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size 142# bit0: 1, Window enabled 143# bit1: 0, Write Protect disabled 144# bit3-2: 00, CS0 hit selected 145# bit23-4: ones, required 146# bit31-24: 0x07, Size (i.e. 128MB) 147 148DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb 149DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 150 151DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 152DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 153 154DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) 155DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 156# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 157# bit3-2: 01, ODT1 active NEVER! 158# bit31-4: zero, required 159 160DATA 0xFFD0149C 0x0000E803 # CPU ODT Control 161DATA 0xFFD01480 0x00000001 # DDR Initialization Control 162#bit0=1, enable DDR init upon this register write 163 164# End of Header extension 165DATA 0x0 0x0 166