1# 2# Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu> 3# 4# Based on sheevaplug/kwbimage.cfg originally written by 5# Prafulla Wadaskar <prafulla@marvell.com> 6# (C) Copyright 2009 7# Marvell Semiconductor <www.marvell.com> 8# 9# SPDX-License-Identifier: GPL-2.0+ 10# 11# Refer doc/README.kwbimage for more details about how-to configure 12# and create kirkwood boot image 13# 14 15# Boot Media configurations 16BOOT_FROM nand 17NAND_ECC_MODE default 18NAND_PAGE_SIZE 0x0800 19 20# SOC registers configuration using bootrom header extension 21# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 22 23# Configure RGMII-0 interface pad voltage to 1.8V 24DATA 0xFFD100e0 0x1b1b1b9b 25 26#Dram initalization for SINGLE x16 CL=5 @ 400MHz 27DATA 0xFFD01400 0x43000c30 # DDR Configuration register 28# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 29# bit23-14: zero 30# bit24: 1= enable exit self refresh mode on DDR access 31# bit25: 1 required 32# bit29-26: zero 33# bit31-30: 01 34 35DATA 0xFFD01404 0x37543000 # DDR Controller Control Low 36# bit 4: 0=addr/cmd in smame cycle 37# bit 5: 0=clk is driven during self refresh, we don't care for APX 38# bit 6: 0=use recommended falling edge of clk for addr/cmd 39# bit14: 0=input buffer always powered up 40# bit18: 1=cpu lock transaction enabled 41# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 42# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 43# bit30-28: 3 required 44# bit31: 0=no additional STARTBURST delay 45 46DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) 47# bit3-0: TRAS lsbs 48# bit7-4: TRCD 49# bit11- 8: TRP 50# bit15-12: TWR 51# bit19-16: TWTR 52# bit20: TRAS msb 53# bit23-21: 0x0 54# bit27-24: TRRD 55# bit31-28: TRTP 56 57DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) 58# bit6-0: TRFC 59# bit8-7: TR2R 60# bit10-9: TR2W 61# bit12-11: TW2W 62# bit31-13: zero required 63 64DATA 0xFFD01410 0x0000000d # DDR Address Control 65# bit1-0: 00, Cs0width=x8 66# bit3-2: 11, Cs0size=1Gb 67# bit5-4: 00, Cs1width=nonexistent 68# bit7-6: 00, Cs1size =nonexistent 69# bit9-8: 00, Cs2width=nonexistent 70# bit11-10: 00, Cs2size =nonexistent 71# bit13-12: 00, Cs3width=nonexistent 72# bit15-14: 00, Cs3size =nonexistent 73# bit16: 0, Cs0AddrSel 74# bit17: 0, Cs1AddrSel 75# bit18: 0, Cs2AddrSel 76# bit19: 0, Cs3AddrSel 77# bit31-20: 0 required 78 79DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 80# bit0: 0, OpenPage enabled 81# bit31-1: 0 required 82 83DATA 0xFFD01418 0x00000000 # DDR Operation 84# bit3-0: 0x0, DDR cmd 85# bit31-4: 0 required 86 87DATA 0xFFD0141C 0x00000C52 # DDR Mode 88# bit2-0: 2, BurstLen=2 required 89# bit3: 0, BurstType=0 required 90# bit6-4: 4, CL=5 91# bit7: 0, TestMode=0 normal 92# bit8: 0, DLL reset=0 normal 93# bit11-9: 6, auto-precharge write recovery ???????????? 94# bit12: 0, PD must be zero 95# bit31-13: 0 required 96 97DATA 0xFFD01420 0x00000040 # DDR Extended Mode 98# bit0: 0, DDR DLL enabled 99# bit1: 0, DDR drive strenght normal 100# bit2: 0, DDR ODT control lsd (disabled) 101# bit5-3: 000, required 102# bit6: 1, DDR ODT control msb, (disabled) 103# bit9-7: 000, required 104# bit10: 0, differential DQS enabled 105# bit11: 0, required 106# bit12: 0, DDR output buffer enabled 107# bit31-13: 0 required 108 109DATA 0xFFD01424 0x0000F17F # DDR Controller Control High 110# bit2-0: 111, required 111# bit3 : 1 , MBUS Burst Chop disabled 112# bit6-4: 111, required 113# bit7 : 0 114# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz 115# bit9 : 0 , no half clock cycle addition to dataout 116# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 117# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 118# bit15-12: 1111 required 119# bit31-16: 0 required 120 121DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) 122DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) 123 124DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 125DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size 126# bit0: 1, Window enabled 127# bit1: 0, Write Protect disabled 128# bit3-2: 00, CS0 hit selected 129# bit23-4: ones, required 130# bit31-24: 0x07, Size (i.e. 128MB) 131 132DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb 133DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 134 135DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 136DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 137 138DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) 139DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 140# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 141# bit3-2: 01, ODT1 active NEVER! 142# bit31-4: zero, required 143 144DATA 0xFFD0149C 0x0000E803 # CPU ODT Control 145DATA 0xFFD01480 0x00000001 # DDR Initialization Control 146#bit0=1, enable DDR init upon this register write 147 148# End of Header extension 149DATA 0x0 0x0 150