1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 238041db7SEric Cooper /* 338041db7SEric Cooper * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu> 438041db7SEric Cooper * 538041db7SEric Cooper * Based on sheevaplug.c originally written by 638041db7SEric Cooper * Prafulla Wadaskar <prafulla@marvell.com> 738041db7SEric Cooper * (C) Copyright 2009 838041db7SEric Cooper * Marvell Semiconductor <www.marvell.com> 938041db7SEric Cooper */ 1038041db7SEric Cooper 1138041db7SEric Cooper #include <common.h> 1238041db7SEric Cooper #include <miiphy.h> 133dc23f78SStefan Roese #include <asm/arch/soc.h> 1438041db7SEric Cooper #include <asm/arch/mpp.h> 1536aaa918SAnatolij Gustschin #include <asm/arch/cpu.h> 1636aaa918SAnatolij Gustschin #include <asm/io.h> 17c62db35dSSimon Glass #include <asm/mach-types.h> 1838041db7SEric Cooper #include "dockstar.h" 1938041db7SEric Cooper 2038041db7SEric Cooper DECLARE_GLOBAL_DATA_PTR; 2138041db7SEric Cooper 2238041db7SEric Cooper int board_early_init_f(void) 2338041db7SEric Cooper { 2438041db7SEric Cooper /* 2538041db7SEric Cooper * default gpio configuration 2638041db7SEric Cooper * There are maximum 64 gpios controlled through 2 sets of registers 2738041db7SEric Cooper * the below configuration configures mainly initial LED status 2838041db7SEric Cooper */ 29d5c5132fSStefan Roese mvebu_config_gpio(DOCKSTAR_OE_VAL_LOW, 3038041db7SEric Cooper DOCKSTAR_OE_VAL_HIGH, 3138041db7SEric Cooper DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH); 3238041db7SEric Cooper 3338041db7SEric Cooper /* Multi-Purpose Pins Functionality configuration */ 349d86f0c3SAlbert ARIBAUD static const u32 kwmpp_config[] = { 3538041db7SEric Cooper MPP0_NF_IO2, 3638041db7SEric Cooper MPP1_NF_IO3, 3738041db7SEric Cooper MPP2_NF_IO4, 3838041db7SEric Cooper MPP3_NF_IO5, 3938041db7SEric Cooper MPP4_NF_IO6, 4038041db7SEric Cooper MPP5_NF_IO7, 4138041db7SEric Cooper MPP6_SYSRST_OUTn, 4238041db7SEric Cooper MPP7_GPO, 4338041db7SEric Cooper MPP8_UART0_RTS, 4438041db7SEric Cooper MPP9_UART0_CTS, 4538041db7SEric Cooper MPP10_UART0_TXD, 4638041db7SEric Cooper MPP11_UART0_RXD, 4738041db7SEric Cooper MPP12_SD_CLK, 4838041db7SEric Cooper MPP13_SD_CMD, 4938041db7SEric Cooper MPP14_SD_D0, 5038041db7SEric Cooper MPP15_SD_D1, 5138041db7SEric Cooper MPP16_SD_D2, 5238041db7SEric Cooper MPP17_SD_D3, 5338041db7SEric Cooper MPP18_NF_IO0, 5438041db7SEric Cooper MPP19_NF_IO1, 5538041db7SEric Cooper MPP20_GPIO, 5638041db7SEric Cooper MPP21_GPIO, 5738041db7SEric Cooper MPP22_GPIO, 5838041db7SEric Cooper MPP23_GPIO, 5938041db7SEric Cooper MPP24_GPIO, 6038041db7SEric Cooper MPP25_GPIO, 6138041db7SEric Cooper MPP26_GPIO, 6238041db7SEric Cooper MPP27_GPIO, 6338041db7SEric Cooper MPP28_GPIO, 6438041db7SEric Cooper MPP29_TSMP9, 6538041db7SEric Cooper MPP30_GPIO, 6638041db7SEric Cooper MPP31_GPIO, 6738041db7SEric Cooper MPP32_GPIO, 6838041db7SEric Cooper MPP33_GPIO, 6938041db7SEric Cooper MPP34_GPIO, 7038041db7SEric Cooper MPP35_GPIO, 7138041db7SEric Cooper MPP36_GPIO, 7238041db7SEric Cooper MPP37_GPIO, 7338041db7SEric Cooper MPP38_GPIO, 7438041db7SEric Cooper MPP39_GPIO, 7538041db7SEric Cooper MPP40_GPIO, 7638041db7SEric Cooper MPP41_GPIO, 7738041db7SEric Cooper MPP42_GPIO, 7838041db7SEric Cooper MPP43_GPIO, 7938041db7SEric Cooper MPP44_GPIO, 8038041db7SEric Cooper MPP45_GPIO, 8138041db7SEric Cooper MPP46_GPIO, 8238041db7SEric Cooper MPP47_GPIO, 8338041db7SEric Cooper MPP48_GPIO, 8438041db7SEric Cooper MPP49_GPIO, 8538041db7SEric Cooper 0 8638041db7SEric Cooper }; 8784683638SValentin Longchamp kirkwood_mpp_conf(kwmpp_config, NULL); 8838041db7SEric Cooper return 0; 8938041db7SEric Cooper } 9038041db7SEric Cooper 9138041db7SEric Cooper int board_init(void) 9238041db7SEric Cooper { 9338041db7SEric Cooper /* 9438041db7SEric Cooper * arch number of board 9538041db7SEric Cooper */ 9638041db7SEric Cooper gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR; 9738041db7SEric Cooper 9838041db7SEric Cooper /* address of boot parameters */ 9996c5f081SStefan Roese gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 10038041db7SEric Cooper 10138041db7SEric Cooper return 0; 10238041db7SEric Cooper } 10338041db7SEric Cooper 10438041db7SEric Cooper #ifdef CONFIG_RESET_PHY_R 10538041db7SEric Cooper /* Configure and enable MV88E1116 PHY */ 10638041db7SEric Cooper void reset_phy(void) 10738041db7SEric Cooper { 10838041db7SEric Cooper u16 reg; 10938041db7SEric Cooper u16 devadr; 11038041db7SEric Cooper char *name = "egiga0"; 11138041db7SEric Cooper 11238041db7SEric Cooper if (miiphy_set_current_dev(name)) 11338041db7SEric Cooper return; 11438041db7SEric Cooper 11538041db7SEric Cooper /* command to read PHY dev address */ 11638041db7SEric Cooper if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { 11738041db7SEric Cooper printf("Err..%s could not read PHY dev address\n", 11838041db7SEric Cooper __FUNCTION__); 11938041db7SEric Cooper return; 12038041db7SEric Cooper } 12138041db7SEric Cooper 12238041db7SEric Cooper /* 12338041db7SEric Cooper * Enable RGMII delay on Tx and Rx for CPU port 12438041db7SEric Cooper * Ref: sec 4.7.2 of chip datasheet 12538041db7SEric Cooper */ 12638041db7SEric Cooper miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); 12738041db7SEric Cooper miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); 12838041db7SEric Cooper reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); 12938041db7SEric Cooper miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); 13038041db7SEric Cooper miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); 13138041db7SEric Cooper 13238041db7SEric Cooper /* reset the phy */ 13338041db7SEric Cooper miiphy_reset(name, devadr); 13438041db7SEric Cooper 13538041db7SEric Cooper printf("88E1116 Initialized on %s\n", name); 13638041db7SEric Cooper } 13738041db7SEric Cooper #endif /* CONFIG_RESET_PHY_R */ 13838041db7SEric Cooper 13938041db7SEric Cooper #define GREEN_LED (1 << 14) 14038041db7SEric Cooper #define ORANGE_LED (1 << 15) 14138041db7SEric Cooper #define BOTH_LEDS (GREEN_LED | ORANGE_LED) 14238041db7SEric Cooper #define NEITHER_LED 0 14338041db7SEric Cooper 14438041db7SEric Cooper static void set_leds(u32 leds, u32 blinking) 14538041db7SEric Cooper { 146d5c5132fSStefan Roese struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; 14738041db7SEric Cooper u32 oe = readl(&r->oe) | BOTH_LEDS; 14838041db7SEric Cooper writel(oe & ~leds, &r->oe); /* active low */ 14938041db7SEric Cooper u32 bl = readl(&r->blink_en) & ~BOTH_LEDS; 15038041db7SEric Cooper writel(bl | blinking, &r->blink_en); 15138041db7SEric Cooper } 15238041db7SEric Cooper 15338041db7SEric Cooper void show_boot_progress(int val) 15438041db7SEric Cooper { 15538041db7SEric Cooper switch (val) { 156578ac1e9SSimon Glass case BOOTSTAGE_ID_RUN_OS: /* booting Linux */ 15738041db7SEric Cooper set_leds(BOTH_LEDS, NEITHER_LED); 15838041db7SEric Cooper break; 159c8e66db7SSimon Glass case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */ 16038041db7SEric Cooper set_leds(GREEN_LED, GREEN_LED); 16138041db7SEric Cooper break; 16238041db7SEric Cooper default: 16338041db7SEric Cooper if (val < 0) /* error */ 16438041db7SEric Cooper set_leds(ORANGE_LED, ORANGE_LED); 16538041db7SEric Cooper break; 16638041db7SEric Cooper } 16738041db7SEric Cooper } 168