155dd4ba5SPrafulla Wadaskar /* 255dd4ba5SPrafulla Wadaskar * (C) Copyright 2009 355dd4ba5SPrafulla Wadaskar * Marvell Semiconductor <www.marvell.com> 455dd4ba5SPrafulla Wadaskar * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 555dd4ba5SPrafulla Wadaskar * 655dd4ba5SPrafulla Wadaskar * See file CREDITS for list of people who contributed to this 755dd4ba5SPrafulla Wadaskar * project. 855dd4ba5SPrafulla Wadaskar * 955dd4ba5SPrafulla Wadaskar * This program is free software; you can redistribute it and/or 1055dd4ba5SPrafulla Wadaskar * modify it under the terms of the GNU General Public License as 1155dd4ba5SPrafulla Wadaskar * published by the Free Software Foundation; either version 2 of 1255dd4ba5SPrafulla Wadaskar * the License, or (at your option) any later version. 1355dd4ba5SPrafulla Wadaskar * 1455dd4ba5SPrafulla Wadaskar * This program is distributed in the hope that it will be useful, 1555dd4ba5SPrafulla Wadaskar * but WITHOUT ANY WARRANTY; without even the implied warranty of 1655dd4ba5SPrafulla Wadaskar * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1755dd4ba5SPrafulla Wadaskar * GNU General Public License for more details. 1855dd4ba5SPrafulla Wadaskar * 1955dd4ba5SPrafulla Wadaskar * You should have received a copy of the GNU General Public License 2055dd4ba5SPrafulla Wadaskar * along with this program; if not, write to the Free Software 2155dd4ba5SPrafulla Wadaskar * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 2255dd4ba5SPrafulla Wadaskar * MA 02110-1301 USA 2355dd4ba5SPrafulla Wadaskar */ 2455dd4ba5SPrafulla Wadaskar 2555dd4ba5SPrafulla Wadaskar #include <common.h> 2655dd4ba5SPrafulla Wadaskar #include <miiphy.h> 27a7efd719SLei Wen #include <asm/arch/cpu.h> 2855dd4ba5SPrafulla Wadaskar #include <asm/arch/kirkwood.h> 2955dd4ba5SPrafulla Wadaskar #include <asm/arch/mpp.h> 3055dd4ba5SPrafulla Wadaskar #include "sheevaplug.h" 3155dd4ba5SPrafulla Wadaskar 3255dd4ba5SPrafulla Wadaskar DECLARE_GLOBAL_DATA_PTR; 3355dd4ba5SPrafulla Wadaskar 34754ae3fbSPrafulla Wadaskar int board_early_init_f(void) 3555dd4ba5SPrafulla Wadaskar { 3655dd4ba5SPrafulla Wadaskar /* 3755dd4ba5SPrafulla Wadaskar * default gpio configuration 3855dd4ba5SPrafulla Wadaskar * There are maximum 64 gpios controlled through 2 sets of registers 3955dd4ba5SPrafulla Wadaskar * the below configuration configures mainly initial LED status 4055dd4ba5SPrafulla Wadaskar */ 4155dd4ba5SPrafulla Wadaskar kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW, 4255dd4ba5SPrafulla Wadaskar SHEEVAPLUG_OE_VAL_HIGH, 4355dd4ba5SPrafulla Wadaskar SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH); 4455dd4ba5SPrafulla Wadaskar 4555dd4ba5SPrafulla Wadaskar /* Multi-Purpose Pins Functionality configuration */ 4655dd4ba5SPrafulla Wadaskar u32 kwmpp_config[] = { 4755dd4ba5SPrafulla Wadaskar MPP0_NF_IO2, 4855dd4ba5SPrafulla Wadaskar MPP1_NF_IO3, 4955dd4ba5SPrafulla Wadaskar MPP2_NF_IO4, 5055dd4ba5SPrafulla Wadaskar MPP3_NF_IO5, 5155dd4ba5SPrafulla Wadaskar MPP4_NF_IO6, 5255dd4ba5SPrafulla Wadaskar MPP5_NF_IO7, 5355dd4ba5SPrafulla Wadaskar MPP6_SYSRST_OUTn, 5455dd4ba5SPrafulla Wadaskar MPP7_GPO, 5555dd4ba5SPrafulla Wadaskar MPP8_UART0_RTS, 5655dd4ba5SPrafulla Wadaskar MPP9_UART0_CTS, 5755dd4ba5SPrafulla Wadaskar MPP10_UART0_TXD, 5855dd4ba5SPrafulla Wadaskar MPP11_UART0_RXD, 5955dd4ba5SPrafulla Wadaskar MPP12_SD_CLK, 6055dd4ba5SPrafulla Wadaskar MPP13_SD_CMD, 6155dd4ba5SPrafulla Wadaskar MPP14_SD_D0, 6255dd4ba5SPrafulla Wadaskar MPP15_SD_D1, 6355dd4ba5SPrafulla Wadaskar MPP16_SD_D2, 6455dd4ba5SPrafulla Wadaskar MPP17_SD_D3, 6555dd4ba5SPrafulla Wadaskar MPP18_NF_IO0, 6655dd4ba5SPrafulla Wadaskar MPP19_NF_IO1, 6755dd4ba5SPrafulla Wadaskar MPP20_GPIO, 6855dd4ba5SPrafulla Wadaskar MPP21_GPIO, 6955dd4ba5SPrafulla Wadaskar MPP22_GPIO, 7055dd4ba5SPrafulla Wadaskar MPP23_GPIO, 7155dd4ba5SPrafulla Wadaskar MPP24_GPIO, 7255dd4ba5SPrafulla Wadaskar MPP25_GPIO, 7355dd4ba5SPrafulla Wadaskar MPP26_GPIO, 7455dd4ba5SPrafulla Wadaskar MPP27_GPIO, 7555dd4ba5SPrafulla Wadaskar MPP28_GPIO, 7655dd4ba5SPrafulla Wadaskar MPP29_TSMP9, 7755dd4ba5SPrafulla Wadaskar MPP30_GPIO, 7855dd4ba5SPrafulla Wadaskar MPP31_GPIO, 7955dd4ba5SPrafulla Wadaskar MPP32_GPIO, 8055dd4ba5SPrafulla Wadaskar MPP33_GPIO, 8155dd4ba5SPrafulla Wadaskar MPP34_GPIO, 8255dd4ba5SPrafulla Wadaskar MPP35_GPIO, 8355dd4ba5SPrafulla Wadaskar MPP36_GPIO, 8455dd4ba5SPrafulla Wadaskar MPP37_GPIO, 8555dd4ba5SPrafulla Wadaskar MPP38_GPIO, 8655dd4ba5SPrafulla Wadaskar MPP39_GPIO, 8755dd4ba5SPrafulla Wadaskar MPP40_GPIO, 8855dd4ba5SPrafulla Wadaskar MPP41_GPIO, 8955dd4ba5SPrafulla Wadaskar MPP42_GPIO, 9055dd4ba5SPrafulla Wadaskar MPP43_GPIO, 9155dd4ba5SPrafulla Wadaskar MPP44_GPIO, 9255dd4ba5SPrafulla Wadaskar MPP45_GPIO, 9355dd4ba5SPrafulla Wadaskar MPP46_GPIO, 9455dd4ba5SPrafulla Wadaskar MPP47_GPIO, 9555dd4ba5SPrafulla Wadaskar MPP48_GPIO, 9655dd4ba5SPrafulla Wadaskar MPP49_GPIO, 9755dd4ba5SPrafulla Wadaskar 0 9855dd4ba5SPrafulla Wadaskar }; 99*84683638SValentin Longchamp kirkwood_mpp_conf(kwmpp_config, NULL); 100754ae3fbSPrafulla Wadaskar return 0; 101754ae3fbSPrafulla Wadaskar } 10255dd4ba5SPrafulla Wadaskar 103754ae3fbSPrafulla Wadaskar int board_init(void) 104754ae3fbSPrafulla Wadaskar { 10555dd4ba5SPrafulla Wadaskar /* 10655dd4ba5SPrafulla Wadaskar * arch number of board 10755dd4ba5SPrafulla Wadaskar */ 10855dd4ba5SPrafulla Wadaskar gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG; 10955dd4ba5SPrafulla Wadaskar 11055dd4ba5SPrafulla Wadaskar /* adress of boot parameters */ 11155dd4ba5SPrafulla Wadaskar gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 11255dd4ba5SPrafulla Wadaskar 11355dd4ba5SPrafulla Wadaskar return 0; 11455dd4ba5SPrafulla Wadaskar } 11555dd4ba5SPrafulla Wadaskar 11655dd4ba5SPrafulla Wadaskar #ifdef CONFIG_RESET_PHY_R 11755dd4ba5SPrafulla Wadaskar /* Configure and enable MV88E1116 PHY */ 11855dd4ba5SPrafulla Wadaskar void reset_phy(void) 11955dd4ba5SPrafulla Wadaskar { 12055dd4ba5SPrafulla Wadaskar u16 reg; 12155dd4ba5SPrafulla Wadaskar u16 devadr; 12255dd4ba5SPrafulla Wadaskar char *name = "egiga0"; 12355dd4ba5SPrafulla Wadaskar 12455dd4ba5SPrafulla Wadaskar if (miiphy_set_current_dev(name)) 12555dd4ba5SPrafulla Wadaskar return; 12655dd4ba5SPrafulla Wadaskar 12755dd4ba5SPrafulla Wadaskar /* command to read PHY dev address */ 12855dd4ba5SPrafulla Wadaskar if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { 12955dd4ba5SPrafulla Wadaskar printf("Err..%s could not read PHY dev address\n", 13055dd4ba5SPrafulla Wadaskar __FUNCTION__); 13155dd4ba5SPrafulla Wadaskar return; 13255dd4ba5SPrafulla Wadaskar } 13355dd4ba5SPrafulla Wadaskar 13455dd4ba5SPrafulla Wadaskar /* 13555dd4ba5SPrafulla Wadaskar * Enable RGMII delay on Tx and Rx for CPU port 13655dd4ba5SPrafulla Wadaskar * Ref: sec 4.7.2 of chip datasheet 13755dd4ba5SPrafulla Wadaskar */ 13855dd4ba5SPrafulla Wadaskar miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); 13955dd4ba5SPrafulla Wadaskar miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); 14055dd4ba5SPrafulla Wadaskar reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); 14155dd4ba5SPrafulla Wadaskar miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); 14255dd4ba5SPrafulla Wadaskar miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); 14355dd4ba5SPrafulla Wadaskar 14455dd4ba5SPrafulla Wadaskar /* reset the phy */ 14555dd4ba5SPrafulla Wadaskar miiphy_reset(name, devadr); 14655dd4ba5SPrafulla Wadaskar 14755dd4ba5SPrafulla Wadaskar printf("88E1116 Initialized on %s\n", name); 14855dd4ba5SPrafulla Wadaskar } 14955dd4ba5SPrafulla Wadaskar #endif /* CONFIG_RESET_PHY_R */ 150