1*55dd4ba5SPrafulla Wadaskar /* 2*55dd4ba5SPrafulla Wadaskar * (C) Copyright 2009 3*55dd4ba5SPrafulla Wadaskar * Marvell Semiconductor <www.marvell.com> 4*55dd4ba5SPrafulla Wadaskar * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5*55dd4ba5SPrafulla Wadaskar * 6*55dd4ba5SPrafulla Wadaskar * See file CREDITS for list of people who contributed to this 7*55dd4ba5SPrafulla Wadaskar * project. 8*55dd4ba5SPrafulla Wadaskar * 9*55dd4ba5SPrafulla Wadaskar * This program is free software; you can redistribute it and/or 10*55dd4ba5SPrafulla Wadaskar * modify it under the terms of the GNU General Public License as 11*55dd4ba5SPrafulla Wadaskar * published by the Free Software Foundation; either version 2 of 12*55dd4ba5SPrafulla Wadaskar * the License, or (at your option) any later version. 13*55dd4ba5SPrafulla Wadaskar * 14*55dd4ba5SPrafulla Wadaskar * This program is distributed in the hope that it will be useful, 15*55dd4ba5SPrafulla Wadaskar * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*55dd4ba5SPrafulla Wadaskar * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*55dd4ba5SPrafulla Wadaskar * GNU General Public License for more details. 18*55dd4ba5SPrafulla Wadaskar * 19*55dd4ba5SPrafulla Wadaskar * You should have received a copy of the GNU General Public License 20*55dd4ba5SPrafulla Wadaskar * along with this program; if not, write to the Free Software 21*55dd4ba5SPrafulla Wadaskar * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 22*55dd4ba5SPrafulla Wadaskar * MA 02110-1301 USA 23*55dd4ba5SPrafulla Wadaskar */ 24*55dd4ba5SPrafulla Wadaskar 25*55dd4ba5SPrafulla Wadaskar #include <common.h> 26*55dd4ba5SPrafulla Wadaskar #include <miiphy.h> 27*55dd4ba5SPrafulla Wadaskar #include <asm/arch/kirkwood.h> 28*55dd4ba5SPrafulla Wadaskar #include <asm/arch/mpp.h> 29*55dd4ba5SPrafulla Wadaskar #include "sheevaplug.h" 30*55dd4ba5SPrafulla Wadaskar 31*55dd4ba5SPrafulla Wadaskar DECLARE_GLOBAL_DATA_PTR; 32*55dd4ba5SPrafulla Wadaskar 33*55dd4ba5SPrafulla Wadaskar int board_init(void) 34*55dd4ba5SPrafulla Wadaskar { 35*55dd4ba5SPrafulla Wadaskar /* 36*55dd4ba5SPrafulla Wadaskar * default gpio configuration 37*55dd4ba5SPrafulla Wadaskar * There are maximum 64 gpios controlled through 2 sets of registers 38*55dd4ba5SPrafulla Wadaskar * the below configuration configures mainly initial LED status 39*55dd4ba5SPrafulla Wadaskar */ 40*55dd4ba5SPrafulla Wadaskar kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW, 41*55dd4ba5SPrafulla Wadaskar SHEEVAPLUG_OE_VAL_HIGH, 42*55dd4ba5SPrafulla Wadaskar SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH); 43*55dd4ba5SPrafulla Wadaskar 44*55dd4ba5SPrafulla Wadaskar /* Multi-Purpose Pins Functionality configuration */ 45*55dd4ba5SPrafulla Wadaskar u32 kwmpp_config[] = { 46*55dd4ba5SPrafulla Wadaskar MPP0_NF_IO2, 47*55dd4ba5SPrafulla Wadaskar MPP1_NF_IO3, 48*55dd4ba5SPrafulla Wadaskar MPP2_NF_IO4, 49*55dd4ba5SPrafulla Wadaskar MPP3_NF_IO5, 50*55dd4ba5SPrafulla Wadaskar MPP4_NF_IO6, 51*55dd4ba5SPrafulla Wadaskar MPP5_NF_IO7, 52*55dd4ba5SPrafulla Wadaskar MPP6_SYSRST_OUTn, 53*55dd4ba5SPrafulla Wadaskar MPP7_GPO, 54*55dd4ba5SPrafulla Wadaskar MPP8_UART0_RTS, 55*55dd4ba5SPrafulla Wadaskar MPP9_UART0_CTS, 56*55dd4ba5SPrafulla Wadaskar MPP10_UART0_TXD, 57*55dd4ba5SPrafulla Wadaskar MPP11_UART0_RXD, 58*55dd4ba5SPrafulla Wadaskar MPP12_SD_CLK, 59*55dd4ba5SPrafulla Wadaskar MPP13_SD_CMD, 60*55dd4ba5SPrafulla Wadaskar MPP14_SD_D0, 61*55dd4ba5SPrafulla Wadaskar MPP15_SD_D1, 62*55dd4ba5SPrafulla Wadaskar MPP16_SD_D2, 63*55dd4ba5SPrafulla Wadaskar MPP17_SD_D3, 64*55dd4ba5SPrafulla Wadaskar MPP18_NF_IO0, 65*55dd4ba5SPrafulla Wadaskar MPP19_NF_IO1, 66*55dd4ba5SPrafulla Wadaskar MPP20_GPIO, 67*55dd4ba5SPrafulla Wadaskar MPP21_GPIO, 68*55dd4ba5SPrafulla Wadaskar MPP22_GPIO, 69*55dd4ba5SPrafulla Wadaskar MPP23_GPIO, 70*55dd4ba5SPrafulla Wadaskar MPP24_GPIO, 71*55dd4ba5SPrafulla Wadaskar MPP25_GPIO, 72*55dd4ba5SPrafulla Wadaskar MPP26_GPIO, 73*55dd4ba5SPrafulla Wadaskar MPP27_GPIO, 74*55dd4ba5SPrafulla Wadaskar MPP28_GPIO, 75*55dd4ba5SPrafulla Wadaskar MPP29_TSMP9, 76*55dd4ba5SPrafulla Wadaskar MPP30_GPIO, 77*55dd4ba5SPrafulla Wadaskar MPP31_GPIO, 78*55dd4ba5SPrafulla Wadaskar MPP32_GPIO, 79*55dd4ba5SPrafulla Wadaskar MPP33_GPIO, 80*55dd4ba5SPrafulla Wadaskar MPP34_GPIO, 81*55dd4ba5SPrafulla Wadaskar MPP35_GPIO, 82*55dd4ba5SPrafulla Wadaskar MPP36_GPIO, 83*55dd4ba5SPrafulla Wadaskar MPP37_GPIO, 84*55dd4ba5SPrafulla Wadaskar MPP38_GPIO, 85*55dd4ba5SPrafulla Wadaskar MPP39_GPIO, 86*55dd4ba5SPrafulla Wadaskar MPP40_GPIO, 87*55dd4ba5SPrafulla Wadaskar MPP41_GPIO, 88*55dd4ba5SPrafulla Wadaskar MPP42_GPIO, 89*55dd4ba5SPrafulla Wadaskar MPP43_GPIO, 90*55dd4ba5SPrafulla Wadaskar MPP44_GPIO, 91*55dd4ba5SPrafulla Wadaskar MPP45_GPIO, 92*55dd4ba5SPrafulla Wadaskar MPP46_GPIO, 93*55dd4ba5SPrafulla Wadaskar MPP47_GPIO, 94*55dd4ba5SPrafulla Wadaskar MPP48_GPIO, 95*55dd4ba5SPrafulla Wadaskar MPP49_GPIO, 96*55dd4ba5SPrafulla Wadaskar 0 97*55dd4ba5SPrafulla Wadaskar }; 98*55dd4ba5SPrafulla Wadaskar kirkwood_mpp_conf(kwmpp_config); 99*55dd4ba5SPrafulla Wadaskar 100*55dd4ba5SPrafulla Wadaskar /* 101*55dd4ba5SPrafulla Wadaskar * arch number of board 102*55dd4ba5SPrafulla Wadaskar */ 103*55dd4ba5SPrafulla Wadaskar gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG; 104*55dd4ba5SPrafulla Wadaskar 105*55dd4ba5SPrafulla Wadaskar /* adress of boot parameters */ 106*55dd4ba5SPrafulla Wadaskar gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 107*55dd4ba5SPrafulla Wadaskar 108*55dd4ba5SPrafulla Wadaskar return 0; 109*55dd4ba5SPrafulla Wadaskar } 110*55dd4ba5SPrafulla Wadaskar 111*55dd4ba5SPrafulla Wadaskar int dram_init(void) 112*55dd4ba5SPrafulla Wadaskar { 113*55dd4ba5SPrafulla Wadaskar int i; 114*55dd4ba5SPrafulla Wadaskar 115*55dd4ba5SPrafulla Wadaskar for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 116*55dd4ba5SPrafulla Wadaskar gd->bd->bi_dram[i].start = kw_sdram_bar(i); 117*55dd4ba5SPrafulla Wadaskar gd->bd->bi_dram[i].size = kw_sdram_bs(i); 118*55dd4ba5SPrafulla Wadaskar } 119*55dd4ba5SPrafulla Wadaskar return 0; 120*55dd4ba5SPrafulla Wadaskar } 121*55dd4ba5SPrafulla Wadaskar 122*55dd4ba5SPrafulla Wadaskar #ifdef CONFIG_RESET_PHY_R 123*55dd4ba5SPrafulla Wadaskar /* Configure and enable MV88E1116 PHY */ 124*55dd4ba5SPrafulla Wadaskar void reset_phy(void) 125*55dd4ba5SPrafulla Wadaskar { 126*55dd4ba5SPrafulla Wadaskar u16 reg; 127*55dd4ba5SPrafulla Wadaskar u16 devadr; 128*55dd4ba5SPrafulla Wadaskar char *name = "egiga0"; 129*55dd4ba5SPrafulla Wadaskar 130*55dd4ba5SPrafulla Wadaskar if (miiphy_set_current_dev(name)) 131*55dd4ba5SPrafulla Wadaskar return; 132*55dd4ba5SPrafulla Wadaskar 133*55dd4ba5SPrafulla Wadaskar /* command to read PHY dev address */ 134*55dd4ba5SPrafulla Wadaskar if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { 135*55dd4ba5SPrafulla Wadaskar printf("Err..%s could not read PHY dev address\n", 136*55dd4ba5SPrafulla Wadaskar __FUNCTION__); 137*55dd4ba5SPrafulla Wadaskar return; 138*55dd4ba5SPrafulla Wadaskar } 139*55dd4ba5SPrafulla Wadaskar 140*55dd4ba5SPrafulla Wadaskar /* 141*55dd4ba5SPrafulla Wadaskar * Enable RGMII delay on Tx and Rx for CPU port 142*55dd4ba5SPrafulla Wadaskar * Ref: sec 4.7.2 of chip datasheet 143*55dd4ba5SPrafulla Wadaskar */ 144*55dd4ba5SPrafulla Wadaskar miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); 145*55dd4ba5SPrafulla Wadaskar miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); 146*55dd4ba5SPrafulla Wadaskar reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); 147*55dd4ba5SPrafulla Wadaskar miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); 148*55dd4ba5SPrafulla Wadaskar miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); 149*55dd4ba5SPrafulla Wadaskar 150*55dd4ba5SPrafulla Wadaskar /* reset the phy */ 151*55dd4ba5SPrafulla Wadaskar miiphy_reset(name, devadr); 152*55dd4ba5SPrafulla Wadaskar 153*55dd4ba5SPrafulla Wadaskar printf("88E1116 Initialized on %s\n", name); 154*55dd4ba5SPrafulla Wadaskar } 155*55dd4ba5SPrafulla Wadaskar #endif /* CONFIG_RESET_PHY_R */ 156