1 /* 2 * (C) Copyright 2009 3 * Net Insight <www.netinsight.net> 4 * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> 5 * 6 * Based on sheevaplug.c: 7 * (C) Copyright 2009 8 * Marvell Semiconductor <www.marvell.com> 9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <miiphy.h> 16 #include <asm/mach-types.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/soc.h> 19 #include <asm/arch/mpp.h> 20 #include "openrd.h" 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 int board_early_init_f(void) 25 { 26 /* 27 * default gpio configuration 28 * There are maximum 64 gpios controlled through 2 sets of registers 29 * the below configuration configures mainly initial LED status 30 */ 31 mvebu_config_gpio(OPENRD_OE_VAL_LOW, 32 OPENRD_OE_VAL_HIGH, 33 OPENRD_OE_LOW, OPENRD_OE_HIGH); 34 35 /* Multi-Purpose Pins Functionality configuration */ 36 static const u32 kwmpp_config[] = { 37 MPP0_NF_IO2, 38 MPP1_NF_IO3, 39 MPP2_NF_IO4, 40 MPP3_NF_IO5, 41 MPP4_NF_IO6, 42 MPP5_NF_IO7, 43 MPP6_SYSRST_OUTn, 44 MPP7_GPO, 45 MPP8_TW_SDA, 46 MPP9_TW_SCK, 47 MPP10_UART0_TXD, 48 MPP11_UART0_RXD, 49 MPP12_SD_CLK, 50 MPP13_SD_CMD, /* Alt UART1_TXD */ 51 MPP14_SD_D0, /* Alt UART1_RXD */ 52 MPP15_SD_D1, 53 MPP16_SD_D2, 54 MPP17_SD_D3, 55 MPP18_NF_IO0, 56 MPP19_NF_IO1, 57 MPP20_GE1_0, 58 MPP21_GE1_1, 59 MPP22_GE1_2, 60 MPP23_GE1_3, 61 MPP24_GE1_4, 62 MPP25_GE1_5, 63 MPP26_GE1_6, 64 MPP27_GE1_7, 65 MPP28_GPIO, 66 MPP29_TSMP9, 67 MPP30_GE1_10, 68 MPP31_GE1_11, 69 MPP32_GE1_12, 70 MPP33_GE1_13, 71 MPP34_GPIO, /* UART1 / SD sel */ 72 MPP35_TDM_CH0_TX_QL, 73 MPP36_TDM_SPI_CS1, 74 MPP37_TDM_CH2_TX_QL, 75 MPP38_TDM_CH2_RX_QL, 76 MPP39_AUDIO_I2SBCLK, 77 MPP40_AUDIO_I2SDO, 78 MPP41_AUDIO_I2SLRC, 79 MPP42_AUDIO_I2SMCLK, 80 MPP43_AUDIO_I2SDI, 81 MPP44_AUDIO_EXTCLK, 82 MPP45_TDM_PCLK, 83 MPP46_TDM_FS, 84 MPP47_TDM_DRX, 85 MPP48_TDM_DTX, 86 MPP49_TDM_CH0_RX_QL, 87 0 88 }; 89 90 kirkwood_mpp_conf(kwmpp_config, NULL); 91 return 0; 92 } 93 94 int board_init(void) 95 { 96 /* 97 * arch number of board 98 */ 99 #if defined(CONFIG_BOARD_IS_OPENRD_BASE) 100 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; 101 #elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT) 102 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT; 103 #elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) 104 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE; 105 #endif 106 107 /* adress of boot parameters */ 108 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 109 return 0; 110 } 111 112 #ifdef CONFIG_RESET_PHY_R 113 /* Configure and enable MV88E1116/88E1121 PHY */ 114 void mv_phy_init(char *name) 115 { 116 u16 reg; 117 u16 devadr; 118 119 if (miiphy_set_current_dev(name)) 120 return; 121 122 /* command to read PHY dev address */ 123 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { 124 printf("Err..%s could not read PHY dev address\n", __func__); 125 return; 126 } 127 128 /* 129 * Enable RGMII delay on Tx and Rx for CPU port 130 * Ref: sec 4.7.2 of chip datasheet 131 */ 132 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); 133 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); 134 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); 135 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); 136 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); 137 138 /* reset the phy */ 139 miiphy_reset(name, devadr); 140 141 printf(PHY_NO" Initialized on %s\n", name); 142 } 143 144 void reset_phy(void) 145 { 146 mv_phy_init("egiga0"); 147 148 #ifdef CONFIG_BOARD_IS_OPENRD_CLIENT 149 /* Kirkwood ethernet driver is written with the assumption that in case 150 * of multiple PHYs, their addresses are consecutive. But unfortunately 151 * in case of OpenRD-Client, PHY addresses are not consecutive.*/ 152 miiphy_write("egiga1", 0xEE, 0xEE, 24); 153 #endif 154 155 #if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \ 156 defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) 157 /* configure and initialize both PHY's */ 158 mv_phy_init("egiga1"); 159 #endif 160 } 161 #endif /* CONFIG_RESET_PHY_R */ 162