1 /* 2 * (C) Copyright 2009 3 * Net Insight <www.netinsight.net> 4 * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> 5 * 6 * Based on sheevaplug.c: 7 * (C) Copyright 2009 8 * Marvell Semiconductor <www.marvell.com> 9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 27 * MA 02110-1301 USA 28 */ 29 30 #include <common.h> 31 #include <miiphy.h> 32 #include <asm/arch/cpu.h> 33 #include <asm/arch/kirkwood.h> 34 #include <asm/arch/mpp.h> 35 #include "openrd.h" 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 int board_early_init_f(void) 40 { 41 /* 42 * default gpio configuration 43 * There are maximum 64 gpios controlled through 2 sets of registers 44 * the below configuration configures mainly initial LED status 45 */ 46 kw_config_gpio(OPENRD_OE_VAL_LOW, 47 OPENRD_OE_VAL_HIGH, 48 OPENRD_OE_LOW, OPENRD_OE_HIGH); 49 50 /* Multi-Purpose Pins Functionality configuration */ 51 u32 kwmpp_config[] = { 52 MPP0_NF_IO2, 53 MPP1_NF_IO3, 54 MPP2_NF_IO4, 55 MPP3_NF_IO5, 56 MPP4_NF_IO6, 57 MPP5_NF_IO7, 58 MPP6_SYSRST_OUTn, 59 MPP7_GPO, 60 MPP8_TW_SDA, 61 MPP9_TW_SCK, 62 MPP10_UART0_TXD, 63 MPP11_UART0_RXD, 64 MPP12_SD_CLK, 65 MPP13_SD_CMD, /* Alt UART1_TXD */ 66 MPP14_SD_D0, /* Alt UART1_RXD */ 67 MPP15_SD_D1, 68 MPP16_SD_D2, 69 MPP17_SD_D3, 70 MPP18_NF_IO0, 71 MPP19_NF_IO1, 72 MPP20_GE1_0, 73 MPP21_GE1_1, 74 MPP22_GE1_2, 75 MPP23_GE1_3, 76 MPP24_GE1_4, 77 MPP25_GE1_5, 78 MPP26_GE1_6, 79 MPP27_GE1_7, 80 MPP28_GPIO, 81 MPP29_TSMP9, 82 MPP30_GE1_10, 83 MPP31_GE1_11, 84 MPP32_GE1_12, 85 MPP33_GE1_13, 86 MPP34_GPIO, /* UART1 / SD sel */ 87 MPP35_TDM_CH0_TX_QL, 88 MPP36_TDM_SPI_CS1, 89 MPP37_TDM_CH2_TX_QL, 90 MPP38_TDM_CH2_RX_QL, 91 MPP39_AUDIO_I2SBCLK, 92 MPP40_AUDIO_I2SDO, 93 MPP41_AUDIO_I2SLRC, 94 MPP42_AUDIO_I2SMCLK, 95 MPP43_AUDIO_I2SDI, 96 MPP44_AUDIO_EXTCLK, 97 MPP45_TDM_PCLK, 98 MPP46_TDM_FS, 99 MPP47_TDM_DRX, 100 MPP48_TDM_DTX, 101 MPP49_TDM_CH0_RX_QL, 102 0 103 }; 104 105 kirkwood_mpp_conf(kwmpp_config, NULL); 106 return 0; 107 } 108 109 int board_init(void) 110 { 111 /* 112 * arch number of board 113 */ 114 #if defined(CONFIG_BOARD_IS_OPENRD_BASE) 115 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; 116 #elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT) 117 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT; 118 #elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) 119 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE; 120 #endif 121 122 /* adress of boot parameters */ 123 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 124 return 0; 125 } 126 127 #ifdef CONFIG_RESET_PHY_R 128 /* Configure and enable MV88E1116/88E1121 PHY */ 129 void mv_phy_init(char *name) 130 { 131 u16 reg; 132 u16 devadr; 133 134 if (miiphy_set_current_dev(name)) 135 return; 136 137 /* command to read PHY dev address */ 138 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { 139 printf("Err..%s could not read PHY dev address\n", 140 __FUNCTION__); 141 return; 142 } 143 144 /* 145 * Enable RGMII delay on Tx and Rx for CPU port 146 * Ref: sec 4.7.2 of chip datasheet 147 */ 148 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); 149 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); 150 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); 151 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); 152 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); 153 154 /* reset the phy */ 155 miiphy_reset(name, devadr); 156 157 printf(PHY_NO" Initialized on %s\n", name); 158 } 159 160 void reset_phy(void) 161 { 162 mv_phy_init("egiga0"); 163 164 #ifdef CONFIG_BOARD_IS_OPENRD_CLIENT 165 /* Kirkwood ethernet driver is written with the assumption that in case 166 * of multiple PHYs, their addresses are consecutive. But unfortunately 167 * in case of OpenRD-Client, PHY addresses are not consecutive.*/ 168 miiphy_write("egiga1", 0xEE, 0xEE, 24); 169 #endif 170 171 #if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \ 172 defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) 173 /* configure and initialize both PHY's */ 174 mv_phy_init("egiga1"); 175 #endif 176 } 177 #endif /* CONFIG_RESET_PHY_R */ 178