1 /* 2 * (C) Copyright 2009 3 * Net Insight <www.netinsight.net> 4 * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> 5 * 6 * Based on sheevaplug.c: 7 * (C) Copyright 2009 8 * Marvell Semiconductor <www.marvell.com> 9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 27 * MA 02110-1301 USA 28 */ 29 30 #include <common.h> 31 #include <miiphy.h> 32 #include <asm/arch/kirkwood.h> 33 #include <asm/arch/mpp.h> 34 #include "openrd.h" 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 int board_early_init_f(void) 39 { 40 /* 41 * default gpio configuration 42 * There are maximum 64 gpios controlled through 2 sets of registers 43 * the below configuration configures mainly initial LED status 44 */ 45 kw_config_gpio(OPENRD_OE_VAL_LOW, 46 OPENRD_OE_VAL_HIGH, 47 OPENRD_OE_LOW, OPENRD_OE_HIGH); 48 49 /* Multi-Purpose Pins Functionality configuration */ 50 u32 kwmpp_config[] = { 51 MPP0_NF_IO2, 52 MPP1_NF_IO3, 53 MPP2_NF_IO4, 54 MPP3_NF_IO5, 55 MPP4_NF_IO6, 56 MPP5_NF_IO7, 57 MPP6_SYSRST_OUTn, 58 MPP7_GPO, 59 MPP8_TW_SDA, 60 MPP9_TW_SCK, 61 MPP10_UART0_TXD, 62 MPP11_UART0_RXD, 63 MPP12_SD_CLK, 64 MPP13_SD_CMD, /* Alt UART1_TXD */ 65 MPP14_SD_D0, /* Alt UART1_RXD */ 66 MPP15_SD_D1, 67 MPP16_SD_D2, 68 MPP17_SD_D3, 69 MPP18_NF_IO0, 70 MPP19_NF_IO1, 71 MPP20_GE1_0, 72 MPP21_GE1_1, 73 MPP22_GE1_2, 74 MPP23_GE1_3, 75 MPP24_GE1_4, 76 MPP25_GE1_5, 77 MPP26_GE1_6, 78 MPP27_GE1_7, 79 MPP28_GPIO, 80 MPP29_TSMP9, 81 MPP30_GE1_10, 82 MPP31_GE1_11, 83 MPP32_GE1_12, 84 MPP33_GE1_13, 85 MPP34_GPIO, /* UART1 / SD sel */ 86 MPP35_TDM_CH0_TX_QL, 87 MPP36_TDM_SPI_CS1, 88 MPP37_TDM_CH2_TX_QL, 89 MPP38_TDM_CH2_RX_QL, 90 MPP39_AUDIO_I2SBCLK, 91 MPP40_AUDIO_I2SDO, 92 MPP41_AUDIO_I2SLRC, 93 MPP42_AUDIO_I2SMCLK, 94 MPP43_AUDIO_I2SDI, 95 MPP44_AUDIO_EXTCLK, 96 MPP45_TDM_PCLK, 97 MPP46_TDM_FS, 98 MPP47_TDM_DRX, 99 MPP48_TDM_DTX, 100 MPP49_TDM_CH0_RX_QL, 101 0 102 }; 103 104 kirkwood_mpp_conf(kwmpp_config); 105 return 0; 106 } 107 108 int board_init(void) 109 { 110 /* 111 * arch number of board 112 */ 113 #if defined(CONFIG_BOARD_IS_OPENRD_BASE) 114 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; 115 #elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT) 116 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT; 117 #elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) 118 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE; 119 #endif 120 121 /* adress of boot parameters */ 122 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 123 return 0; 124 } 125 126 #ifdef CONFIG_RESET_PHY_R 127 /* Configure and enable MV88E1116/88E1121 PHY */ 128 void mv_phy_init(char *name) 129 { 130 u16 reg; 131 u16 devadr; 132 133 if (miiphy_set_current_dev(name)) 134 return; 135 136 /* command to read PHY dev address */ 137 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { 138 printf("Err..%s could not read PHY dev address\n", 139 __FUNCTION__); 140 return; 141 } 142 143 /* 144 * Enable RGMII delay on Tx and Rx for CPU port 145 * Ref: sec 4.7.2 of chip datasheet 146 */ 147 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); 148 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); 149 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); 150 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); 151 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); 152 153 /* reset the phy */ 154 miiphy_reset(name, devadr); 155 156 printf(PHY_NO" Initialized on %s\n", name); 157 } 158 159 void reset_phy(void) 160 { 161 mv_phy_init("egiga0"); 162 163 #ifdef CONFIG_BOARD_IS_OPENRD_CLIENT 164 /* Kirkwood ethernet driver is written with the assumption that in case 165 * of multiple PHYs, their addresses are consecutive. But unfortunately 166 * in case of OpenRD-Client, PHY addresses are not consecutive.*/ 167 miiphy_write("egiga1", 0xEE, 0xEE, 24); 168 #endif 169 170 #if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \ 171 defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) 172 /* configure and initialize both PHY's */ 173 mv_phy_init("egiga1"); 174 #endif 175 } 176 #endif /* CONFIG_RESET_PHY_R */ 177