135629363SAlbert ARIBAUD /* 235629363SAlbert ARIBAUD * (C) Copyright 2009 335629363SAlbert ARIBAUD * Net Insight <www.netinsight.net> 435629363SAlbert ARIBAUD * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> 535629363SAlbert ARIBAUD * 635629363SAlbert ARIBAUD * Based on sheevaplug.c: 735629363SAlbert ARIBAUD * (C) Copyright 2009 835629363SAlbert ARIBAUD * Marvell Semiconductor <www.marvell.com> 935629363SAlbert ARIBAUD * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 1035629363SAlbert ARIBAUD * 1135629363SAlbert ARIBAUD * SPDX-License-Identifier: GPL-2.0+ 1235629363SAlbert ARIBAUD */ 1335629363SAlbert ARIBAUD 1435629363SAlbert ARIBAUD #include <common.h> 1535629363SAlbert ARIBAUD #include <miiphy.h> 16*c62db35dSSimon Glass #include <asm/mach-types.h> 1735629363SAlbert ARIBAUD #include <asm/arch/cpu.h> 1835629363SAlbert ARIBAUD #include <asm/arch/soc.h> 1935629363SAlbert ARIBAUD #include <asm/arch/mpp.h> 2035629363SAlbert ARIBAUD #include "openrd.h" 2135629363SAlbert ARIBAUD 2235629363SAlbert ARIBAUD DECLARE_GLOBAL_DATA_PTR; 2335629363SAlbert ARIBAUD 2435629363SAlbert ARIBAUD int board_early_init_f(void) 2535629363SAlbert ARIBAUD { 2635629363SAlbert ARIBAUD /* 2735629363SAlbert ARIBAUD * default gpio configuration 2835629363SAlbert ARIBAUD * There are maximum 64 gpios controlled through 2 sets of registers 2935629363SAlbert ARIBAUD * the below configuration configures mainly initial LED status 3035629363SAlbert ARIBAUD */ 3135629363SAlbert ARIBAUD mvebu_config_gpio(OPENRD_OE_VAL_LOW, 3235629363SAlbert ARIBAUD OPENRD_OE_VAL_HIGH, 3335629363SAlbert ARIBAUD OPENRD_OE_LOW, OPENRD_OE_HIGH); 3435629363SAlbert ARIBAUD 3535629363SAlbert ARIBAUD /* Multi-Purpose Pins Functionality configuration */ 3635629363SAlbert ARIBAUD static const u32 kwmpp_config[] = { 3735629363SAlbert ARIBAUD MPP0_NF_IO2, 3835629363SAlbert ARIBAUD MPP1_NF_IO3, 3935629363SAlbert ARIBAUD MPP2_NF_IO4, 4035629363SAlbert ARIBAUD MPP3_NF_IO5, 4135629363SAlbert ARIBAUD MPP4_NF_IO6, 4235629363SAlbert ARIBAUD MPP5_NF_IO7, 4335629363SAlbert ARIBAUD MPP6_SYSRST_OUTn, 4435629363SAlbert ARIBAUD MPP7_GPO, 4535629363SAlbert ARIBAUD MPP8_TW_SDA, 4635629363SAlbert ARIBAUD MPP9_TW_SCK, 4735629363SAlbert ARIBAUD MPP10_UART0_TXD, 4835629363SAlbert ARIBAUD MPP11_UART0_RXD, 4935629363SAlbert ARIBAUD MPP12_SD_CLK, 5035629363SAlbert ARIBAUD MPP13_SD_CMD, /* Alt UART1_TXD */ 5135629363SAlbert ARIBAUD MPP14_SD_D0, /* Alt UART1_RXD */ 5235629363SAlbert ARIBAUD MPP15_SD_D1, 5335629363SAlbert ARIBAUD MPP16_SD_D2, 5435629363SAlbert ARIBAUD MPP17_SD_D3, 5535629363SAlbert ARIBAUD MPP18_NF_IO0, 5635629363SAlbert ARIBAUD MPP19_NF_IO1, 5735629363SAlbert ARIBAUD MPP20_GE1_0, 5835629363SAlbert ARIBAUD MPP21_GE1_1, 5935629363SAlbert ARIBAUD MPP22_GE1_2, 6035629363SAlbert ARIBAUD MPP23_GE1_3, 6135629363SAlbert ARIBAUD MPP24_GE1_4, 6235629363SAlbert ARIBAUD MPP25_GE1_5, 6335629363SAlbert ARIBAUD MPP26_GE1_6, 6435629363SAlbert ARIBAUD MPP27_GE1_7, 6535629363SAlbert ARIBAUD MPP28_GPIO, 6635629363SAlbert ARIBAUD MPP29_TSMP9, 6735629363SAlbert ARIBAUD MPP30_GE1_10, 6835629363SAlbert ARIBAUD MPP31_GE1_11, 6935629363SAlbert ARIBAUD MPP32_GE1_12, 7035629363SAlbert ARIBAUD MPP33_GE1_13, 7135629363SAlbert ARIBAUD MPP34_GPIO, /* UART1 / SD sel */ 7235629363SAlbert ARIBAUD MPP35_TDM_CH0_TX_QL, 7335629363SAlbert ARIBAUD MPP36_TDM_SPI_CS1, 7435629363SAlbert ARIBAUD MPP37_TDM_CH2_TX_QL, 7535629363SAlbert ARIBAUD MPP38_TDM_CH2_RX_QL, 7635629363SAlbert ARIBAUD MPP39_AUDIO_I2SBCLK, 7735629363SAlbert ARIBAUD MPP40_AUDIO_I2SDO, 7835629363SAlbert ARIBAUD MPP41_AUDIO_I2SLRC, 7935629363SAlbert ARIBAUD MPP42_AUDIO_I2SMCLK, 8035629363SAlbert ARIBAUD MPP43_AUDIO_I2SDI, 8135629363SAlbert ARIBAUD MPP44_AUDIO_EXTCLK, 8235629363SAlbert ARIBAUD MPP45_TDM_PCLK, 8335629363SAlbert ARIBAUD MPP46_TDM_FS, 8435629363SAlbert ARIBAUD MPP47_TDM_DRX, 8535629363SAlbert ARIBAUD MPP48_TDM_DTX, 8635629363SAlbert ARIBAUD MPP49_TDM_CH0_RX_QL, 8735629363SAlbert ARIBAUD 0 8835629363SAlbert ARIBAUD }; 8935629363SAlbert ARIBAUD 9035629363SAlbert ARIBAUD kirkwood_mpp_conf(kwmpp_config, NULL); 9135629363SAlbert ARIBAUD return 0; 9235629363SAlbert ARIBAUD } 9335629363SAlbert ARIBAUD 9435629363SAlbert ARIBAUD int board_init(void) 9535629363SAlbert ARIBAUD { 9635629363SAlbert ARIBAUD /* 9735629363SAlbert ARIBAUD * arch number of board 9835629363SAlbert ARIBAUD */ 9935629363SAlbert ARIBAUD #if defined(CONFIG_BOARD_IS_OPENRD_BASE) 10035629363SAlbert ARIBAUD gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; 10135629363SAlbert ARIBAUD #elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT) 10235629363SAlbert ARIBAUD gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT; 10335629363SAlbert ARIBAUD #elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) 10435629363SAlbert ARIBAUD gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE; 10535629363SAlbert ARIBAUD #endif 10635629363SAlbert ARIBAUD 10735629363SAlbert ARIBAUD /* adress of boot parameters */ 10835629363SAlbert ARIBAUD gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 10935629363SAlbert ARIBAUD return 0; 11035629363SAlbert ARIBAUD } 11135629363SAlbert ARIBAUD 11235629363SAlbert ARIBAUD #ifdef CONFIG_RESET_PHY_R 11335629363SAlbert ARIBAUD /* Configure and enable MV88E1116/88E1121 PHY */ 11435629363SAlbert ARIBAUD void mv_phy_init(char *name) 11535629363SAlbert ARIBAUD { 11635629363SAlbert ARIBAUD u16 reg; 11735629363SAlbert ARIBAUD u16 devadr; 11835629363SAlbert ARIBAUD 11935629363SAlbert ARIBAUD if (miiphy_set_current_dev(name)) 12035629363SAlbert ARIBAUD return; 12135629363SAlbert ARIBAUD 12235629363SAlbert ARIBAUD /* command to read PHY dev address */ 12335629363SAlbert ARIBAUD if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { 12435629363SAlbert ARIBAUD printf("Err..%s could not read PHY dev address\n", __func__); 12535629363SAlbert ARIBAUD return; 12635629363SAlbert ARIBAUD } 12735629363SAlbert ARIBAUD 12835629363SAlbert ARIBAUD /* 12935629363SAlbert ARIBAUD * Enable RGMII delay on Tx and Rx for CPU port 13035629363SAlbert ARIBAUD * Ref: sec 4.7.2 of chip datasheet 13135629363SAlbert ARIBAUD */ 13235629363SAlbert ARIBAUD miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); 13335629363SAlbert ARIBAUD miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); 13435629363SAlbert ARIBAUD reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); 13535629363SAlbert ARIBAUD miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); 13635629363SAlbert ARIBAUD miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); 13735629363SAlbert ARIBAUD 13835629363SAlbert ARIBAUD /* reset the phy */ 13935629363SAlbert ARIBAUD miiphy_reset(name, devadr); 14035629363SAlbert ARIBAUD 14135629363SAlbert ARIBAUD printf(PHY_NO" Initialized on %s\n", name); 14235629363SAlbert ARIBAUD } 14335629363SAlbert ARIBAUD 14435629363SAlbert ARIBAUD void reset_phy(void) 14535629363SAlbert ARIBAUD { 14635629363SAlbert ARIBAUD mv_phy_init("egiga0"); 14735629363SAlbert ARIBAUD 14835629363SAlbert ARIBAUD #ifdef CONFIG_BOARD_IS_OPENRD_CLIENT 14935629363SAlbert ARIBAUD /* Kirkwood ethernet driver is written with the assumption that in case 15035629363SAlbert ARIBAUD * of multiple PHYs, their addresses are consecutive. But unfortunately 15135629363SAlbert ARIBAUD * in case of OpenRD-Client, PHY addresses are not consecutive.*/ 15235629363SAlbert ARIBAUD miiphy_write("egiga1", 0xEE, 0xEE, 24); 15335629363SAlbert ARIBAUD #endif 15435629363SAlbert ARIBAUD 15535629363SAlbert ARIBAUD #if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \ 15635629363SAlbert ARIBAUD defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) 15735629363SAlbert ARIBAUD /* configure and initialize both PHY's */ 15835629363SAlbert ARIBAUD mv_phy_init("egiga1"); 15935629363SAlbert ARIBAUD #endif 16035629363SAlbert ARIBAUD } 16135629363SAlbert ARIBAUD #endif /* CONFIG_RESET_PHY_R */ 162