1*35629363SAlbert ARIBAUD /* 2*35629363SAlbert ARIBAUD * (C) Copyright 2009 3*35629363SAlbert ARIBAUD * Net Insight <www.netinsight.net> 4*35629363SAlbert ARIBAUD * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> 5*35629363SAlbert ARIBAUD * 6*35629363SAlbert ARIBAUD * Based on sheevaplug.c: 7*35629363SAlbert ARIBAUD * (C) Copyright 2009 8*35629363SAlbert ARIBAUD * Marvell Semiconductor <www.marvell.com> 9*35629363SAlbert ARIBAUD * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 10*35629363SAlbert ARIBAUD * 11*35629363SAlbert ARIBAUD * SPDX-License-Identifier: GPL-2.0+ 12*35629363SAlbert ARIBAUD */ 13*35629363SAlbert ARIBAUD 14*35629363SAlbert ARIBAUD #include <common.h> 15*35629363SAlbert ARIBAUD #include <miiphy.h> 16*35629363SAlbert ARIBAUD #include <asm/arch/cpu.h> 17*35629363SAlbert ARIBAUD #include <asm/arch/soc.h> 18*35629363SAlbert ARIBAUD #include <asm/arch/mpp.h> 19*35629363SAlbert ARIBAUD #include "openrd.h" 20*35629363SAlbert ARIBAUD 21*35629363SAlbert ARIBAUD DECLARE_GLOBAL_DATA_PTR; 22*35629363SAlbert ARIBAUD 23*35629363SAlbert ARIBAUD int board_early_init_f(void) 24*35629363SAlbert ARIBAUD { 25*35629363SAlbert ARIBAUD /* 26*35629363SAlbert ARIBAUD * default gpio configuration 27*35629363SAlbert ARIBAUD * There are maximum 64 gpios controlled through 2 sets of registers 28*35629363SAlbert ARIBAUD * the below configuration configures mainly initial LED status 29*35629363SAlbert ARIBAUD */ 30*35629363SAlbert ARIBAUD mvebu_config_gpio(OPENRD_OE_VAL_LOW, 31*35629363SAlbert ARIBAUD OPENRD_OE_VAL_HIGH, 32*35629363SAlbert ARIBAUD OPENRD_OE_LOW, OPENRD_OE_HIGH); 33*35629363SAlbert ARIBAUD 34*35629363SAlbert ARIBAUD /* Multi-Purpose Pins Functionality configuration */ 35*35629363SAlbert ARIBAUD static const u32 kwmpp_config[] = { 36*35629363SAlbert ARIBAUD MPP0_NF_IO2, 37*35629363SAlbert ARIBAUD MPP1_NF_IO3, 38*35629363SAlbert ARIBAUD MPP2_NF_IO4, 39*35629363SAlbert ARIBAUD MPP3_NF_IO5, 40*35629363SAlbert ARIBAUD MPP4_NF_IO6, 41*35629363SAlbert ARIBAUD MPP5_NF_IO7, 42*35629363SAlbert ARIBAUD MPP6_SYSRST_OUTn, 43*35629363SAlbert ARIBAUD MPP7_GPO, 44*35629363SAlbert ARIBAUD MPP8_TW_SDA, 45*35629363SAlbert ARIBAUD MPP9_TW_SCK, 46*35629363SAlbert ARIBAUD MPP10_UART0_TXD, 47*35629363SAlbert ARIBAUD MPP11_UART0_RXD, 48*35629363SAlbert ARIBAUD MPP12_SD_CLK, 49*35629363SAlbert ARIBAUD MPP13_SD_CMD, /* Alt UART1_TXD */ 50*35629363SAlbert ARIBAUD MPP14_SD_D0, /* Alt UART1_RXD */ 51*35629363SAlbert ARIBAUD MPP15_SD_D1, 52*35629363SAlbert ARIBAUD MPP16_SD_D2, 53*35629363SAlbert ARIBAUD MPP17_SD_D3, 54*35629363SAlbert ARIBAUD MPP18_NF_IO0, 55*35629363SAlbert ARIBAUD MPP19_NF_IO1, 56*35629363SAlbert ARIBAUD MPP20_GE1_0, 57*35629363SAlbert ARIBAUD MPP21_GE1_1, 58*35629363SAlbert ARIBAUD MPP22_GE1_2, 59*35629363SAlbert ARIBAUD MPP23_GE1_3, 60*35629363SAlbert ARIBAUD MPP24_GE1_4, 61*35629363SAlbert ARIBAUD MPP25_GE1_5, 62*35629363SAlbert ARIBAUD MPP26_GE1_6, 63*35629363SAlbert ARIBAUD MPP27_GE1_7, 64*35629363SAlbert ARIBAUD MPP28_GPIO, 65*35629363SAlbert ARIBAUD MPP29_TSMP9, 66*35629363SAlbert ARIBAUD MPP30_GE1_10, 67*35629363SAlbert ARIBAUD MPP31_GE1_11, 68*35629363SAlbert ARIBAUD MPP32_GE1_12, 69*35629363SAlbert ARIBAUD MPP33_GE1_13, 70*35629363SAlbert ARIBAUD MPP34_GPIO, /* UART1 / SD sel */ 71*35629363SAlbert ARIBAUD MPP35_TDM_CH0_TX_QL, 72*35629363SAlbert ARIBAUD MPP36_TDM_SPI_CS1, 73*35629363SAlbert ARIBAUD MPP37_TDM_CH2_TX_QL, 74*35629363SAlbert ARIBAUD MPP38_TDM_CH2_RX_QL, 75*35629363SAlbert ARIBAUD MPP39_AUDIO_I2SBCLK, 76*35629363SAlbert ARIBAUD MPP40_AUDIO_I2SDO, 77*35629363SAlbert ARIBAUD MPP41_AUDIO_I2SLRC, 78*35629363SAlbert ARIBAUD MPP42_AUDIO_I2SMCLK, 79*35629363SAlbert ARIBAUD MPP43_AUDIO_I2SDI, 80*35629363SAlbert ARIBAUD MPP44_AUDIO_EXTCLK, 81*35629363SAlbert ARIBAUD MPP45_TDM_PCLK, 82*35629363SAlbert ARIBAUD MPP46_TDM_FS, 83*35629363SAlbert ARIBAUD MPP47_TDM_DRX, 84*35629363SAlbert ARIBAUD MPP48_TDM_DTX, 85*35629363SAlbert ARIBAUD MPP49_TDM_CH0_RX_QL, 86*35629363SAlbert ARIBAUD 0 87*35629363SAlbert ARIBAUD }; 88*35629363SAlbert ARIBAUD 89*35629363SAlbert ARIBAUD kirkwood_mpp_conf(kwmpp_config, NULL); 90*35629363SAlbert ARIBAUD return 0; 91*35629363SAlbert ARIBAUD } 92*35629363SAlbert ARIBAUD 93*35629363SAlbert ARIBAUD int board_init(void) 94*35629363SAlbert ARIBAUD { 95*35629363SAlbert ARIBAUD /* 96*35629363SAlbert ARIBAUD * arch number of board 97*35629363SAlbert ARIBAUD */ 98*35629363SAlbert ARIBAUD #if defined(CONFIG_BOARD_IS_OPENRD_BASE) 99*35629363SAlbert ARIBAUD gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; 100*35629363SAlbert ARIBAUD #elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT) 101*35629363SAlbert ARIBAUD gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT; 102*35629363SAlbert ARIBAUD #elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) 103*35629363SAlbert ARIBAUD gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE; 104*35629363SAlbert ARIBAUD #endif 105*35629363SAlbert ARIBAUD 106*35629363SAlbert ARIBAUD /* adress of boot parameters */ 107*35629363SAlbert ARIBAUD gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 108*35629363SAlbert ARIBAUD return 0; 109*35629363SAlbert ARIBAUD } 110*35629363SAlbert ARIBAUD 111*35629363SAlbert ARIBAUD #ifdef CONFIG_RESET_PHY_R 112*35629363SAlbert ARIBAUD /* Configure and enable MV88E1116/88E1121 PHY */ 113*35629363SAlbert ARIBAUD void mv_phy_init(char *name) 114*35629363SAlbert ARIBAUD { 115*35629363SAlbert ARIBAUD u16 reg; 116*35629363SAlbert ARIBAUD u16 devadr; 117*35629363SAlbert ARIBAUD 118*35629363SAlbert ARIBAUD if (miiphy_set_current_dev(name)) 119*35629363SAlbert ARIBAUD return; 120*35629363SAlbert ARIBAUD 121*35629363SAlbert ARIBAUD /* command to read PHY dev address */ 122*35629363SAlbert ARIBAUD if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { 123*35629363SAlbert ARIBAUD printf("Err..%s could not read PHY dev address\n", __func__); 124*35629363SAlbert ARIBAUD return; 125*35629363SAlbert ARIBAUD } 126*35629363SAlbert ARIBAUD 127*35629363SAlbert ARIBAUD /* 128*35629363SAlbert ARIBAUD * Enable RGMII delay on Tx and Rx for CPU port 129*35629363SAlbert ARIBAUD * Ref: sec 4.7.2 of chip datasheet 130*35629363SAlbert ARIBAUD */ 131*35629363SAlbert ARIBAUD miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); 132*35629363SAlbert ARIBAUD miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); 133*35629363SAlbert ARIBAUD reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); 134*35629363SAlbert ARIBAUD miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); 135*35629363SAlbert ARIBAUD miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); 136*35629363SAlbert ARIBAUD 137*35629363SAlbert ARIBAUD /* reset the phy */ 138*35629363SAlbert ARIBAUD miiphy_reset(name, devadr); 139*35629363SAlbert ARIBAUD 140*35629363SAlbert ARIBAUD printf(PHY_NO" Initialized on %s\n", name); 141*35629363SAlbert ARIBAUD } 142*35629363SAlbert ARIBAUD 143*35629363SAlbert ARIBAUD void reset_phy(void) 144*35629363SAlbert ARIBAUD { 145*35629363SAlbert ARIBAUD mv_phy_init("egiga0"); 146*35629363SAlbert ARIBAUD 147*35629363SAlbert ARIBAUD #ifdef CONFIG_BOARD_IS_OPENRD_CLIENT 148*35629363SAlbert ARIBAUD /* Kirkwood ethernet driver is written with the assumption that in case 149*35629363SAlbert ARIBAUD * of multiple PHYs, their addresses are consecutive. But unfortunately 150*35629363SAlbert ARIBAUD * in case of OpenRD-Client, PHY addresses are not consecutive.*/ 151*35629363SAlbert ARIBAUD miiphy_write("egiga1", 0xEE, 0xEE, 24); 152*35629363SAlbert ARIBAUD #endif 153*35629363SAlbert ARIBAUD 154*35629363SAlbert ARIBAUD #if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \ 155*35629363SAlbert ARIBAUD defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) 156*35629363SAlbert ARIBAUD /* configure and initialize both PHY's */ 157*35629363SAlbert ARIBAUD mv_phy_init("egiga1"); 158*35629363SAlbert ARIBAUD #endif 159*35629363SAlbert ARIBAUD } 160*35629363SAlbert ARIBAUD #endif /* CONFIG_RESET_PHY_R */ 161