1# 2# (C) Copyright 2009 3# Marvell Semiconductor <www.marvell.com> 4# Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5# 6# See file CREDITS for list of people who contributed to this 7# project. 8# 9# This program is free software; you can redistribute it and/or 10# modify it under the terms of the GNU General Public License as 11# published by the Free Software Foundation; either version 2 of 12# the License, or (at your option) any later version. 13# 14# This program is distributed in the hope that it will be useful, 15# but WITHOUT ANY WARRANTY; without even the implied warranty of 16# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17# GNU General Public License for more details. 18# 19# You should have received a copy of the GNU General Public License 20# along with this program; if not, write to the Free Software 21# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 22# MA 02110-1301 USA 23# 24# Refer docs/README.kwimage for more details about how-to configure 25# and create kirkwood boot image 26# 27 28# Boot Media configurations 29BOOT_FROM nand 30NAND_ECC_MODE default 31NAND_PAGE_SIZE 0x0800 32 33# SOC registers configuration using bootrom header extension 34# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 35 36# Configure RGMII-0 interface pad voltage to 1.8V 37DATA 0xFFD100e0 0x1b1b1b9b 38 39#Dram initalization for SINGLE x16 CL=5 @ 400MHz 40DATA 0xFFD01400 0x43000c30 # DDR Configuration register 41# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 42# bit23-14: zero 43# bit24: 1= enable exit self refresh mode on DDR access 44# bit25: 1 required 45# bit29-26: zero 46# bit31-30: 01 47 48DATA 0xFFD01404 0x37543000 # DDR Controller Control Low 49# bit 4: 0=addr/cmd in smame cycle 50# bit 5: 0=clk is driven during self refresh, we don't care for APX 51# bit 6: 0=use recommended falling edge of clk for addr/cmd 52# bit14: 0=input buffer always powered up 53# bit18: 1=cpu lock transaction enabled 54# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 55# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 56# bit30-28: 3 required 57# bit31: 0=no additional STARTBURST delay 58 59DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) 60# bit3-0: TRAS lsbs 61# bit7-4: TRCD 62# bit11- 8: TRP 63# bit15-12: TWR 64# bit19-16: TWTR 65# bit20: TRAS msb 66# bit23-21: 0x0 67# bit27-24: TRRD 68# bit31-28: TRTP 69 70DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) 71# bit6-0: TRFC 72# bit8-7: TR2R 73# bit10-9: TR2W 74# bit12-11: TW2W 75# bit31-13: zero required 76 77DATA 0xFFD01410 0x000000cc # DDR Address Control 78# bit1-0: 00, Cs0width=x8 79# bit3-2: 11, Cs0size=1Gb 80# bit5-4: 00, Cs1width=x8 81# bit7-6: 11, Cs1size=1Gb 82# bit9-8: 00, Cs2width=nonexistent 83# bit11-10: 00, Cs2size =nonexistent 84# bit13-12: 00, Cs3width=nonexistent 85# bit15-14: 00, Cs3size =nonexistent 86# bit16: 0, Cs0AddrSel 87# bit17: 0, Cs1AddrSel 88# bit18: 0, Cs2AddrSel 89# bit19: 0, Cs3AddrSel 90# bit31-20: 0 required 91 92DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 93# bit0: 0, OpenPage enabled 94# bit31-1: 0 required 95 96DATA 0xFFD01418 0x00000000 # DDR Operation 97# bit3-0: 0x0, DDR cmd 98# bit31-4: 0 required 99 100DATA 0xFFD0141C 0x00000C52 # DDR Mode 101# bit2-0: 2, BurstLen=2 required 102# bit3: 0, BurstType=0 required 103# bit6-4: 4, CL=5 104# bit7: 0, TestMode=0 normal 105# bit8: 0, DLL reset=0 normal 106# bit11-9: 6, auto-precharge write recovery ???????????? 107# bit12: 0, PD must be zero 108# bit31-13: 0 required 109 110DATA 0xFFD01420 0x00000042 # DDR Extended Mode 111# bit0: 0, DDR DLL enabled 112# bit1: 1, DDR drive strength reduced 113# bit2: 0, DDR ODT control lsd (disabled) 114# bit5-3: 000, required 115# bit6: 1, DDR ODT control msb, (disabled) 116# bit9-7: 000, required 117# bit10: 0, differential DQS enabled 118# bit11: 0, required 119# bit12: 0, DDR output buffer enabled 120# bit31-13: 0 required 121 122DATA 0xFFD01424 0x0000F17F # DDR Controller Control High 123# bit2-0: 111, required 124# bit3 : 1 , MBUS Burst Chop disabled 125# bit6-4: 111, required 126# bit7 : 0 127# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz 128# bit9 : 0 , no half clock cycle addition to dataout 129# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 130# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 131# bit15-12: 1111 required 132# bit31-16: 0 required 133 134DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) 135DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) 136 137DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 138DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size 139# bit0: 1, Window enabled 140# bit1: 0, Write Protect disabled 141# bit3-2: 00, CS0 hit selected 142# bit23-4: ones, required 143# bit31-24: 0x0F, Size (i.e. 256MB) 144 145DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb 146DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 147 148DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 149DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 150 151DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) 152# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 153# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 154# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. 155# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. 156DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 157 158DATA 0xFFD0149C 0x0000E40f # CPU ODT Control 159# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 160# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm 161# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm 162# bit14: 1, M_STARTBURST_IN ODT: Enabled 163# bit15: 1, DDR IO ODT Unit: Use ODT block 164DATA 0xFFD01480 0x00000001 # DDR Initialization Control 165#bit0=1, enable DDR init upon this register write 166 167# End of Header extension 168DATA 0x0 0x0 169