1#
2# (C) Copyright 2009
3# Marvell Semiconductor <www.marvell.com>
4# Written-by: Siddarth Gore <gores@marvell.com>
5#
6# SPDX-License-Identifier:	GPL-2.0+
7#
8# Refer doc/README.kwbimage for more details about how-to configure
9# and create kirkwood boot image
10#
11
12# Boot Media configurations
13BOOT_FROM	nand
14NAND_ECC_MODE	default
15NAND_PAGE_SIZE	0x0800
16
17# SOC registers configuration using bootrom header extension
18# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
19
20# Configure RGMII-0/1 interface pad voltage to 1.8V
21DATA 0xFFD100e0 0x1b1b9b9b
22
23#Dram initalization for SINGLE x16 CL=5 @ 400MHz
24DATA 0xFFD01400 0x43000c30	# DDR Configuration register
25# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
26# bit23-14: zero
27# bit24: 1= enable exit self refresh mode on DDR access
28# bit25: 1 required
29# bit29-26: zero
30# bit31-30: 01
31
32DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
33# bit 4:    0=addr/cmd in smame cycle
34# bit 5:    0=clk is driven during self refresh, we don't care for APX
35# bit 6:    0=use recommended falling edge of clk for addr/cmd
36# bit14:    0=input buffer always powered up
37# bit18:    1=cpu lock transaction enabled
38# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
39# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
40# bit30-28: 3 required
41# bit31:    0=no additional STARTBURST delay
42
43DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
44# bit3-0:   TRAS lsbs
45# bit7-4:   TRCD
46# bit11- 8: TRP
47# bit15-12: TWR
48# bit19-16: TWTR
49# bit20:    TRAS msb
50# bit23-21: 0x0
51# bit27-24: TRRD
52# bit31-28: TRTP
53
54DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
55# bit6-0:   TRFC
56# bit8-7:   TR2R
57# bit10-9:  TR2W
58# bit12-11: TW2W
59# bit31-13: zero required
60
61DATA 0xFFD01410 0x000000cc	#  DDR Address Control
62# bit1-0:   01, Cs0width=x8
63# bit3-2:   10, Cs0size=1Gb
64# bit5-4:   01, Cs1width=x8
65# bit7-6:   10, Cs1size=1Gb
66# bit9-8:   00, Cs2width=nonexistent
67# bit11-10: 00, Cs2size =nonexistent
68# bit13-12: 00, Cs3width=nonexistent
69# bit15-14: 00, Cs3size =nonexistent
70# bit16:    0,  Cs0AddrSel
71# bit17:    0,  Cs1AddrSel
72# bit18:    0,  Cs2AddrSel
73# bit19:    0,  Cs3AddrSel
74# bit31-20: 0 required
75
76DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
77# bit0:    0,  OpenPage enabled
78# bit31-1: 0 required
79
80DATA 0xFFD01418 0x00000000	#  DDR Operation
81# bit3-0:   0x0, DDR cmd
82# bit31-4:  0 required
83
84DATA 0xFFD0141C 0x00000C52	#  DDR Mode
85# bit2-0:   2, BurstLen=2 required
86# bit3:     0, BurstType=0 required
87# bit6-4:   4, CL=5
88# bit7:     0, TestMode=0 normal
89# bit8:     0, DLL reset=0 normal
90# bit11-9:  6, auto-precharge write recovery ????????????
91# bit12:    0, PD must be zero
92# bit31-13: 0 required
93
94DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
95# bit0:    0,  DDR DLL enabled
96# bit1:    0,  DDR drive strenght normal
97# bit2:    0,  DDR ODT control lsd (disabled)
98# bit5-3:  000, required
99# bit6:    1,  DDR ODT control msb, (disabled)
100# bit9-7:  000, required
101# bit10:   0,  differential DQS enabled
102# bit11:   0, required
103# bit12:   0, DDR output buffer enabled
104# bit31-13: 0 required
105
106DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
107# bit2-0:  111, required
108# bit3  :  1  , MBUS Burst Chop disabled
109# bit6-4:  111, required
110# bit7  :  0
111# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
112# bit9  :  0  , no half clock cycle addition to dataout
113# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
114# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
115# bit15-12: 1111 required
116# bit31-16: 0    required
117
118DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
119DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
120
121DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
122DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
123# bit0:    1,  Window enabled
124# bit1:    0,  Write Protect disabled
125# bit3-2:  00, CS0 hit selected
126# bit23-4: ones, required
127# bit31-24: 0x0F, Size (i.e. 256MB)
128
129DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
130DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
131
132DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
133DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
134
135DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
136DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
137# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
138# bit3-2:  01, ODT1 active NEVER!
139# bit31-4: zero, required
140
141DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
142DATA 0xFFD01480 0x00000001	# DDR Initialization Control
143#bit0=1, enable DDR init upon this register write
144
145# End of Header extension
146DATA 0x0 0x0
147