1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Siddarth Gore <gores@marvell.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 */ 24 25 #include <common.h> 26 #include <miiphy.h> 27 #include <asm/arch/cpu.h> 28 #include <asm/arch/kirkwood.h> 29 #include <asm/arch/mpp.h> 30 #include "guruplug.h" 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 int board_early_init_f(void) 35 { 36 /* 37 * default gpio configuration 38 * There are maximum 64 gpios controlled through 2 sets of registers 39 * the below configuration configures mainly initial LED status 40 */ 41 kw_config_gpio(GURUPLUG_OE_VAL_LOW, 42 GURUPLUG_OE_VAL_HIGH, 43 GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); 44 45 /* Multi-Purpose Pins Functionality configuration */ 46 u32 kwmpp_config[] = { 47 MPP0_NF_IO2, 48 MPP1_NF_IO3, 49 MPP2_NF_IO4, 50 MPP3_NF_IO5, 51 MPP4_NF_IO6, 52 MPP5_NF_IO7, 53 MPP6_SYSRST_OUTn, 54 MPP7_GPO, /* GPIO_RST */ 55 MPP8_TW_SDA, 56 MPP9_TW_SCK, 57 MPP10_UART0_TXD, 58 MPP11_UART0_RXD, 59 MPP12_SD_CLK, 60 MPP13_SD_CMD, 61 MPP14_SD_D0, 62 MPP15_SD_D1, 63 MPP16_SD_D2, 64 MPP17_SD_D3, 65 MPP18_NF_IO0, 66 MPP19_NF_IO1, 67 MPP20_GE1_0, 68 MPP21_GE1_1, 69 MPP22_GE1_2, 70 MPP23_GE1_3, 71 MPP24_GE1_4, 72 MPP25_GE1_5, 73 MPP26_GE1_6, 74 MPP27_GE1_7, 75 MPP28_GE1_8, 76 MPP29_GE1_9, 77 MPP30_GE1_10, 78 MPP31_GE1_11, 79 MPP32_GE1_12, 80 MPP33_GE1_13, 81 MPP34_GE1_14, 82 MPP35_GE1_15, 83 MPP36_GPIO, 84 MPP37_GPIO, 85 MPP38_GPIO, 86 MPP39_GPIO, 87 MPP40_TDM_SPI_SCK, 88 MPP41_TDM_SPI_MISO, 89 MPP42_TDM_SPI_MOSI, 90 MPP43_GPIO, 91 MPP44_GPIO, 92 MPP45_GPIO, 93 MPP46_GPIO, /* M_RLED */ 94 MPP47_GPIO, /* M_GLED */ 95 MPP48_GPIO, /* B_RLED */ 96 MPP49_GPIO, /* B_GLED */ 97 0 98 }; 99 kirkwood_mpp_conf(kwmpp_config); 100 return 0; 101 } 102 103 int board_init(void) 104 { 105 /* 106 * arch number of board 107 */ 108 gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG; 109 110 /* adress of boot parameters */ 111 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 112 113 return 0; 114 } 115 116 #ifdef CONFIG_RESET_PHY_R 117 void mv_phy_88e1121_init(char *name) 118 { 119 u16 reg; 120 u16 devadr; 121 122 if (miiphy_set_current_dev(name)) 123 return; 124 125 /* command to read PHY dev address */ 126 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { 127 printf("Err..%s could not read PHY dev address\n", 128 __FUNCTION__); 129 return; 130 } 131 132 /* 133 * Enable RGMII delay on Tx and Rx for CPU port 134 * Ref: sec 4.7.2 of chip datasheet 135 */ 136 miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2); 137 miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, ®); 138 reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL); 139 miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg); 140 miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0); 141 142 /* reset the phy */ 143 miiphy_reset(name, devadr); 144 145 printf("88E1121 Initialized on %s\n", name); 146 } 147 148 void reset_phy(void) 149 { 150 /* configure and initialize both PHY's */ 151 mv_phy_88e1121_init("egiga0"); 152 mv_phy_88e1121_init("egiga1"); 153 } 154 #endif /* CONFIG_RESET_PHY_R */ 155