1 /*
2  * (C) Copyright 2009
3  * Marvell Semiconductor <www.marvell.com>
4  * Written-by: Siddarth Gore <gores@marvell.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <common.h>
10 #include <miiphy.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13 #include <asm/arch/mpp.h>
14 #include "guruplug.h"
15 
16 DECLARE_GLOBAL_DATA_PTR;
17 
18 int board_early_init_f(void)
19 {
20 	/*
21 	 * default gpio configuration
22 	 * There are maximum 64 gpios controlled through 2 sets of registers
23 	 * the  below configuration configures mainly initial LED status
24 	 */
25 	mvebu_config_gpio(GURUPLUG_OE_VAL_LOW,
26 			  GURUPLUG_OE_VAL_HIGH,
27 			  GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
28 
29 	/* Multi-Purpose Pins Functionality configuration */
30 	static const u32 kwmpp_config[] = {
31 		MPP0_NF_IO2,
32 		MPP1_NF_IO3,
33 		MPP2_NF_IO4,
34 		MPP3_NF_IO5,
35 		MPP4_NF_IO6,
36 		MPP5_NF_IO7,
37 		MPP6_SYSRST_OUTn,
38 		MPP7_GPO,	/* GPIO_RST */
39 		MPP8_TW_SDA,
40 		MPP9_TW_SCK,
41 		MPP10_UART0_TXD,
42 		MPP11_UART0_RXD,
43 		MPP12_SD_CLK,
44 		MPP13_SD_CMD,
45 		MPP14_SD_D0,
46 		MPP15_SD_D1,
47 		MPP16_SD_D2,
48 		MPP17_SD_D3,
49 		MPP18_NF_IO0,
50 		MPP19_NF_IO1,
51 		MPP20_GE1_0,
52 		MPP21_GE1_1,
53 		MPP22_GE1_2,
54 		MPP23_GE1_3,
55 		MPP24_GE1_4,
56 		MPP25_GE1_5,
57 		MPP26_GE1_6,
58 		MPP27_GE1_7,
59 		MPP28_GE1_8,
60 		MPP29_GE1_9,
61 		MPP30_GE1_10,
62 		MPP31_GE1_11,
63 		MPP32_GE1_12,
64 		MPP33_GE1_13,
65 		MPP34_GE1_14,
66 		MPP35_GE1_15,
67 		MPP36_GPIO,
68 		MPP37_GPIO,
69 		MPP38_GPIO,
70 		MPP39_GPIO,
71 		MPP40_TDM_SPI_SCK,
72 		MPP41_TDM_SPI_MISO,
73 		MPP42_TDM_SPI_MOSI,
74 		MPP43_GPIO,
75 		MPP44_GPIO,
76 		MPP45_GPIO,
77 		MPP46_GPIO, 	/* M_RLED */
78 		MPP47_GPIO,	/* M_GLED */
79 		MPP48_GPIO,	/* B_RLED */
80 		MPP49_GPIO,	/* B_GLED */
81 		0
82 	};
83 	kirkwood_mpp_conf(kwmpp_config, NULL);
84 	return 0;
85 }
86 
87 int board_init(void)
88 {
89 	/*
90 	 * arch number of board
91 	 */
92 	gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
93 
94 	/* adress of boot parameters */
95 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
96 
97 	return 0;
98 }
99 
100 #ifdef CONFIG_RESET_PHY_R
101 void mv_phy_88e1121_init(char *name)
102 {
103 	u16 reg;
104 	u16 devadr;
105 
106 	if (miiphy_set_current_dev(name))
107 		return;
108 
109 	/* command to read PHY dev address */
110 	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
111 		printf("Err..%s could not read PHY dev address\n",
112 			__FUNCTION__);
113 		return;
114 	}
115 
116 	/*
117 	 * Enable RGMII delay on Tx and Rx for CPU port
118 	 * Ref: sec 4.7.2 of chip datasheet
119 	 */
120 	miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
121 	miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, &reg);
122 	reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
123 	miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
124 	miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
125 
126 	/* reset the phy */
127 	miiphy_reset(name, devadr);
128 
129 	printf("88E1121 Initialized on %s\n", name);
130 }
131 
132 void reset_phy(void)
133 {
134 	/* configure and initialize both PHY's */
135 	mv_phy_88e1121_init("egiga0");
136 	mv_phy_88e1121_init("egiga1");
137 }
138 #endif /* CONFIG_RESET_PHY_R */
139