1 /*
2  * (C) Copyright 2009
3  * Marvell Semiconductor <www.marvell.com>
4  * Written-by: Siddarth Gore <gores@marvell.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <common.h>
10 #include <miiphy.h>
11 #include <asm/mach-types.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
14 #include <asm/arch/mpp.h>
15 #include "guruplug.h"
16 
17 DECLARE_GLOBAL_DATA_PTR;
18 
19 int board_early_init_f(void)
20 {
21 	/*
22 	 * default gpio configuration
23 	 * There are maximum 64 gpios controlled through 2 sets of registers
24 	 * the  below configuration configures mainly initial LED status
25 	 */
26 	mvebu_config_gpio(GURUPLUG_OE_VAL_LOW,
27 			  GURUPLUG_OE_VAL_HIGH,
28 			  GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
29 
30 	/* Multi-Purpose Pins Functionality configuration */
31 	static const u32 kwmpp_config[] = {
32 		MPP0_NF_IO2,
33 		MPP1_NF_IO3,
34 		MPP2_NF_IO4,
35 		MPP3_NF_IO5,
36 		MPP4_NF_IO6,
37 		MPP5_NF_IO7,
38 		MPP6_SYSRST_OUTn,
39 		MPP7_GPO,	/* GPIO_RST */
40 		MPP8_TW_SDA,
41 		MPP9_TW_SCK,
42 		MPP10_UART0_TXD,
43 		MPP11_UART0_RXD,
44 		MPP12_SD_CLK,
45 		MPP13_SD_CMD,
46 		MPP14_SD_D0,
47 		MPP15_SD_D1,
48 		MPP16_SD_D2,
49 		MPP17_SD_D3,
50 		MPP18_NF_IO0,
51 		MPP19_NF_IO1,
52 		MPP20_GE1_0,
53 		MPP21_GE1_1,
54 		MPP22_GE1_2,
55 		MPP23_GE1_3,
56 		MPP24_GE1_4,
57 		MPP25_GE1_5,
58 		MPP26_GE1_6,
59 		MPP27_GE1_7,
60 		MPP28_GE1_8,
61 		MPP29_GE1_9,
62 		MPP30_GE1_10,
63 		MPP31_GE1_11,
64 		MPP32_GE1_12,
65 		MPP33_GE1_13,
66 		MPP34_GE1_14,
67 		MPP35_GE1_15,
68 		MPP36_GPIO,
69 		MPP37_GPIO,
70 		MPP38_GPIO,
71 		MPP39_GPIO,
72 		MPP40_TDM_SPI_SCK,
73 		MPP41_TDM_SPI_MISO,
74 		MPP42_TDM_SPI_MOSI,
75 		MPP43_GPIO,
76 		MPP44_GPIO,
77 		MPP45_GPIO,
78 		MPP46_GPIO, 	/* M_RLED */
79 		MPP47_GPIO,	/* M_GLED */
80 		MPP48_GPIO,	/* B_RLED */
81 		MPP49_GPIO,	/* B_GLED */
82 		0
83 	};
84 	kirkwood_mpp_conf(kwmpp_config, NULL);
85 	return 0;
86 }
87 
88 int board_init(void)
89 {
90 	/*
91 	 * arch number of board
92 	 */
93 	gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
94 
95 	/* adress of boot parameters */
96 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
97 
98 	return 0;
99 }
100 
101 #ifdef CONFIG_RESET_PHY_R
102 void mv_phy_88e1121_init(char *name)
103 {
104 	u16 reg;
105 	u16 devadr;
106 
107 	if (miiphy_set_current_dev(name))
108 		return;
109 
110 	/* command to read PHY dev address */
111 	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
112 		printf("Err..%s could not read PHY dev address\n",
113 			__FUNCTION__);
114 		return;
115 	}
116 
117 	/*
118 	 * Enable RGMII delay on Tx and Rx for CPU port
119 	 * Ref: sec 4.7.2 of chip datasheet
120 	 */
121 	miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
122 	miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, &reg);
123 	reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
124 	miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
125 	miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
126 
127 	/* reset the phy */
128 	miiphy_reset(name, devadr);
129 
130 	printf("88E1121 Initialized on %s\n", name);
131 }
132 
133 void reset_phy(void)
134 {
135 	/* configure and initialize both PHY's */
136 	mv_phy_88e1121_init("egiga0");
137 	mv_phy_88e1121_init("egiga1");
138 }
139 #endif /* CONFIG_RESET_PHY_R */
140