116b76705SSiddarth Gore /* 216b76705SSiddarth Gore * (C) Copyright 2009 316b76705SSiddarth Gore * Marvell Semiconductor <www.marvell.com> 416b76705SSiddarth Gore * Written-by: Siddarth Gore <gores@marvell.com> 516b76705SSiddarth Gore * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 716b76705SSiddarth Gore */ 816b76705SSiddarth Gore 916b76705SSiddarth Gore #include <common.h> 1016b76705SSiddarth Gore #include <miiphy.h> 11*c62db35dSSimon Glass #include <asm/mach-types.h> 12a7efd719SLei Wen #include <asm/arch/cpu.h> 133dc23f78SStefan Roese #include <asm/arch/soc.h> 1416b76705SSiddarth Gore #include <asm/arch/mpp.h> 1516b76705SSiddarth Gore #include "guruplug.h" 1616b76705SSiddarth Gore 1716b76705SSiddarth Gore DECLARE_GLOBAL_DATA_PTR; 1816b76705SSiddarth Gore 19754ae3fbSPrafulla Wadaskar int board_early_init_f(void) 2016b76705SSiddarth Gore { 2116b76705SSiddarth Gore /* 2216b76705SSiddarth Gore * default gpio configuration 2316b76705SSiddarth Gore * There are maximum 64 gpios controlled through 2 sets of registers 2416b76705SSiddarth Gore * the below configuration configures mainly initial LED status 2516b76705SSiddarth Gore */ 26d5c5132fSStefan Roese mvebu_config_gpio(GURUPLUG_OE_VAL_LOW, 2716b76705SSiddarth Gore GURUPLUG_OE_VAL_HIGH, 2816b76705SSiddarth Gore GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); 2916b76705SSiddarth Gore 3016b76705SSiddarth Gore /* Multi-Purpose Pins Functionality configuration */ 319d86f0c3SAlbert ARIBAUD static const u32 kwmpp_config[] = { 3216b76705SSiddarth Gore MPP0_NF_IO2, 3316b76705SSiddarth Gore MPP1_NF_IO3, 3416b76705SSiddarth Gore MPP2_NF_IO4, 3516b76705SSiddarth Gore MPP3_NF_IO5, 3616b76705SSiddarth Gore MPP4_NF_IO6, 3716b76705SSiddarth Gore MPP5_NF_IO7, 3816b76705SSiddarth Gore MPP6_SYSRST_OUTn, 3916b76705SSiddarth Gore MPP7_GPO, /* GPIO_RST */ 4016b76705SSiddarth Gore MPP8_TW_SDA, 4116b76705SSiddarth Gore MPP9_TW_SCK, 4216b76705SSiddarth Gore MPP10_UART0_TXD, 4316b76705SSiddarth Gore MPP11_UART0_RXD, 4416b76705SSiddarth Gore MPP12_SD_CLK, 4516b76705SSiddarth Gore MPP13_SD_CMD, 4616b76705SSiddarth Gore MPP14_SD_D0, 4716b76705SSiddarth Gore MPP15_SD_D1, 4816b76705SSiddarth Gore MPP16_SD_D2, 4916b76705SSiddarth Gore MPP17_SD_D3, 5016b76705SSiddarth Gore MPP18_NF_IO0, 5116b76705SSiddarth Gore MPP19_NF_IO1, 5216b76705SSiddarth Gore MPP20_GE1_0, 5316b76705SSiddarth Gore MPP21_GE1_1, 5416b76705SSiddarth Gore MPP22_GE1_2, 5516b76705SSiddarth Gore MPP23_GE1_3, 5616b76705SSiddarth Gore MPP24_GE1_4, 5716b76705SSiddarth Gore MPP25_GE1_5, 5816b76705SSiddarth Gore MPP26_GE1_6, 5916b76705SSiddarth Gore MPP27_GE1_7, 6016b76705SSiddarth Gore MPP28_GE1_8, 6116b76705SSiddarth Gore MPP29_GE1_9, 6216b76705SSiddarth Gore MPP30_GE1_10, 6316b76705SSiddarth Gore MPP31_GE1_11, 6416b76705SSiddarth Gore MPP32_GE1_12, 6516b76705SSiddarth Gore MPP33_GE1_13, 6616b76705SSiddarth Gore MPP34_GE1_14, 6716b76705SSiddarth Gore MPP35_GE1_15, 6816b76705SSiddarth Gore MPP36_GPIO, 6916b76705SSiddarth Gore MPP37_GPIO, 7016b76705SSiddarth Gore MPP38_GPIO, 7116b76705SSiddarth Gore MPP39_GPIO, 7216b76705SSiddarth Gore MPP40_TDM_SPI_SCK, 7316b76705SSiddarth Gore MPP41_TDM_SPI_MISO, 7416b76705SSiddarth Gore MPP42_TDM_SPI_MOSI, 7516b76705SSiddarth Gore MPP43_GPIO, 7616b76705SSiddarth Gore MPP44_GPIO, 7716b76705SSiddarth Gore MPP45_GPIO, 7816b76705SSiddarth Gore MPP46_GPIO, /* M_RLED */ 7916b76705SSiddarth Gore MPP47_GPIO, /* M_GLED */ 8016b76705SSiddarth Gore MPP48_GPIO, /* B_RLED */ 8116b76705SSiddarth Gore MPP49_GPIO, /* B_GLED */ 8216b76705SSiddarth Gore 0 8316b76705SSiddarth Gore }; 8484683638SValentin Longchamp kirkwood_mpp_conf(kwmpp_config, NULL); 85754ae3fbSPrafulla Wadaskar return 0; 86754ae3fbSPrafulla Wadaskar } 8716b76705SSiddarth Gore 88754ae3fbSPrafulla Wadaskar int board_init(void) 89754ae3fbSPrafulla Wadaskar { 9016b76705SSiddarth Gore /* 9116b76705SSiddarth Gore * arch number of board 9216b76705SSiddarth Gore */ 9316b76705SSiddarth Gore gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG; 9416b76705SSiddarth Gore 9516b76705SSiddarth Gore /* adress of boot parameters */ 9696c5f081SStefan Roese gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 9716b76705SSiddarth Gore 9816b76705SSiddarth Gore return 0; 9916b76705SSiddarth Gore } 10016b76705SSiddarth Gore 10116b76705SSiddarth Gore #ifdef CONFIG_RESET_PHY_R 10216b76705SSiddarth Gore void mv_phy_88e1121_init(char *name) 10316b76705SSiddarth Gore { 10416b76705SSiddarth Gore u16 reg; 10516b76705SSiddarth Gore u16 devadr; 10616b76705SSiddarth Gore 10716b76705SSiddarth Gore if (miiphy_set_current_dev(name)) 10816b76705SSiddarth Gore return; 10916b76705SSiddarth Gore 11016b76705SSiddarth Gore /* command to read PHY dev address */ 11116b76705SSiddarth Gore if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { 11216b76705SSiddarth Gore printf("Err..%s could not read PHY dev address\n", 11316b76705SSiddarth Gore __FUNCTION__); 11416b76705SSiddarth Gore return; 11516b76705SSiddarth Gore } 11616b76705SSiddarth Gore 11716b76705SSiddarth Gore /* 11816b76705SSiddarth Gore * Enable RGMII delay on Tx and Rx for CPU port 11916b76705SSiddarth Gore * Ref: sec 4.7.2 of chip datasheet 12016b76705SSiddarth Gore */ 12116b76705SSiddarth Gore miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2); 12216b76705SSiddarth Gore miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, ®); 12316b76705SSiddarth Gore reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL); 12416b76705SSiddarth Gore miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg); 12516b76705SSiddarth Gore miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0); 12616b76705SSiddarth Gore 12716b76705SSiddarth Gore /* reset the phy */ 1283f786bb8SMahavir Jain miiphy_reset(name, devadr); 12916b76705SSiddarth Gore 13016b76705SSiddarth Gore printf("88E1121 Initialized on %s\n", name); 13116b76705SSiddarth Gore } 13216b76705SSiddarth Gore 13316b76705SSiddarth Gore void reset_phy(void) 13416b76705SSiddarth Gore { 13516b76705SSiddarth Gore /* configure and initialize both PHY's */ 13616b76705SSiddarth Gore mv_phy_88e1121_init("egiga0"); 13716b76705SSiddarth Gore mv_phy_88e1121_init("egiga1"); 13816b76705SSiddarth Gore } 13916b76705SSiddarth Gore #endif /* CONFIG_RESET_PHY_R */ 140