116b76705SSiddarth Gore /* 216b76705SSiddarth Gore * (C) Copyright 2009 316b76705SSiddarth Gore * Marvell Semiconductor <www.marvell.com> 416b76705SSiddarth Gore * Written-by: Siddarth Gore <gores@marvell.com> 516b76705SSiddarth Gore * 616b76705SSiddarth Gore * See file CREDITS for list of people who contributed to this 716b76705SSiddarth Gore * project. 816b76705SSiddarth Gore * 916b76705SSiddarth Gore * This program is free software; you can redistribute it and/or 1016b76705SSiddarth Gore * modify it under the terms of the GNU General Public License as 1116b76705SSiddarth Gore * published by the Free Software Foundation; either version 2 of 1216b76705SSiddarth Gore * the License, or (at your option) any later version. 1316b76705SSiddarth Gore * 1416b76705SSiddarth Gore * This program is distributed in the hope that it will be useful, 1516b76705SSiddarth Gore * but WITHOUT ANY WARRANTY; without even the implied warranty of 1616b76705SSiddarth Gore * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1716b76705SSiddarth Gore * GNU General Public License for more details. 1816b76705SSiddarth Gore * 1916b76705SSiddarth Gore * You should have received a copy of the GNU General Public License 2016b76705SSiddarth Gore * along with this program; if not, write to the Free Software 2116b76705SSiddarth Gore * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 2216b76705SSiddarth Gore * MA 02110-1301 USA 2316b76705SSiddarth Gore */ 2416b76705SSiddarth Gore 2516b76705SSiddarth Gore #include <common.h> 2616b76705SSiddarth Gore #include <miiphy.h> 2716b76705SSiddarth Gore #include <asm/arch/kirkwood.h> 2816b76705SSiddarth Gore #include <asm/arch/mpp.h> 2916b76705SSiddarth Gore #include "guruplug.h" 3016b76705SSiddarth Gore 3116b76705SSiddarth Gore DECLARE_GLOBAL_DATA_PTR; 3216b76705SSiddarth Gore 3316b76705SSiddarth Gore int board_init(void) 3416b76705SSiddarth Gore { 3516b76705SSiddarth Gore /* 3616b76705SSiddarth Gore * default gpio configuration 3716b76705SSiddarth Gore * There are maximum 64 gpios controlled through 2 sets of registers 3816b76705SSiddarth Gore * the below configuration configures mainly initial LED status 3916b76705SSiddarth Gore */ 4016b76705SSiddarth Gore kw_config_gpio(GURUPLUG_OE_VAL_LOW, 4116b76705SSiddarth Gore GURUPLUG_OE_VAL_HIGH, 4216b76705SSiddarth Gore GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); 4316b76705SSiddarth Gore 4416b76705SSiddarth Gore /* Multi-Purpose Pins Functionality configuration */ 4516b76705SSiddarth Gore u32 kwmpp_config[] = { 4616b76705SSiddarth Gore MPP0_NF_IO2, 4716b76705SSiddarth Gore MPP1_NF_IO3, 4816b76705SSiddarth Gore MPP2_NF_IO4, 4916b76705SSiddarth Gore MPP3_NF_IO5, 5016b76705SSiddarth Gore MPP4_NF_IO6, 5116b76705SSiddarth Gore MPP5_NF_IO7, 5216b76705SSiddarth Gore MPP6_SYSRST_OUTn, 5316b76705SSiddarth Gore MPP7_GPO, /* GPIO_RST */ 5416b76705SSiddarth Gore MPP8_TW_SDA, 5516b76705SSiddarth Gore MPP9_TW_SCK, 5616b76705SSiddarth Gore MPP10_UART0_TXD, 5716b76705SSiddarth Gore MPP11_UART0_RXD, 5816b76705SSiddarth Gore MPP12_SD_CLK, 5916b76705SSiddarth Gore MPP13_SD_CMD, 6016b76705SSiddarth Gore MPP14_SD_D0, 6116b76705SSiddarth Gore MPP15_SD_D1, 6216b76705SSiddarth Gore MPP16_SD_D2, 6316b76705SSiddarth Gore MPP17_SD_D3, 6416b76705SSiddarth Gore MPP18_NF_IO0, 6516b76705SSiddarth Gore MPP19_NF_IO1, 6616b76705SSiddarth Gore MPP20_GE1_0, 6716b76705SSiddarth Gore MPP21_GE1_1, 6816b76705SSiddarth Gore MPP22_GE1_2, 6916b76705SSiddarth Gore MPP23_GE1_3, 7016b76705SSiddarth Gore MPP24_GE1_4, 7116b76705SSiddarth Gore MPP25_GE1_5, 7216b76705SSiddarth Gore MPP26_GE1_6, 7316b76705SSiddarth Gore MPP27_GE1_7, 7416b76705SSiddarth Gore MPP28_GE1_8, 7516b76705SSiddarth Gore MPP29_GE1_9, 7616b76705SSiddarth Gore MPP30_GE1_10, 7716b76705SSiddarth Gore MPP31_GE1_11, 7816b76705SSiddarth Gore MPP32_GE1_12, 7916b76705SSiddarth Gore MPP33_GE1_13, 8016b76705SSiddarth Gore MPP34_GE1_14, 8116b76705SSiddarth Gore MPP35_GE1_15, 8216b76705SSiddarth Gore MPP36_GPIO, 8316b76705SSiddarth Gore MPP37_GPIO, 8416b76705SSiddarth Gore MPP38_GPIO, 8516b76705SSiddarth Gore MPP39_GPIO, 8616b76705SSiddarth Gore MPP40_TDM_SPI_SCK, 8716b76705SSiddarth Gore MPP41_TDM_SPI_MISO, 8816b76705SSiddarth Gore MPP42_TDM_SPI_MOSI, 8916b76705SSiddarth Gore MPP43_GPIO, 9016b76705SSiddarth Gore MPP44_GPIO, 9116b76705SSiddarth Gore MPP45_GPIO, 9216b76705SSiddarth Gore MPP46_GPIO, /* M_RLED */ 9316b76705SSiddarth Gore MPP47_GPIO, /* M_GLED */ 9416b76705SSiddarth Gore MPP48_GPIO, /* B_RLED */ 9516b76705SSiddarth Gore MPP49_GPIO, /* B_GLED */ 9616b76705SSiddarth Gore 0 9716b76705SSiddarth Gore }; 9816b76705SSiddarth Gore kirkwood_mpp_conf(kwmpp_config); 9916b76705SSiddarth Gore 10016b76705SSiddarth Gore /* 10116b76705SSiddarth Gore * arch number of board 10216b76705SSiddarth Gore */ 10316b76705SSiddarth Gore gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG; 10416b76705SSiddarth Gore 10516b76705SSiddarth Gore /* adress of boot parameters */ 10616b76705SSiddarth Gore gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 10716b76705SSiddarth Gore 10816b76705SSiddarth Gore return 0; 10916b76705SSiddarth Gore } 11016b76705SSiddarth Gore 11116b76705SSiddarth Gore int dram_init(void) 11216b76705SSiddarth Gore { 11316b76705SSiddarth Gore int i; 11416b76705SSiddarth Gore 11516b76705SSiddarth Gore for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 11616b76705SSiddarth Gore gd->bd->bi_dram[i].start = kw_sdram_bar(i); 11716b76705SSiddarth Gore gd->bd->bi_dram[i].size = kw_sdram_bs(i); 11816b76705SSiddarth Gore } 11916b76705SSiddarth Gore return 0; 12016b76705SSiddarth Gore } 12116b76705SSiddarth Gore 12216b76705SSiddarth Gore #ifdef CONFIG_RESET_PHY_R 12316b76705SSiddarth Gore void mv_phy_88e1121_init(char *name) 12416b76705SSiddarth Gore { 12516b76705SSiddarth Gore u16 reg; 12616b76705SSiddarth Gore u16 devadr; 12716b76705SSiddarth Gore 12816b76705SSiddarth Gore if (miiphy_set_current_dev(name)) 12916b76705SSiddarth Gore return; 13016b76705SSiddarth Gore 13116b76705SSiddarth Gore /* command to read PHY dev address */ 13216b76705SSiddarth Gore if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { 13316b76705SSiddarth Gore printf("Err..%s could not read PHY dev address\n", 13416b76705SSiddarth Gore __FUNCTION__); 13516b76705SSiddarth Gore return; 13616b76705SSiddarth Gore } 13716b76705SSiddarth Gore 13816b76705SSiddarth Gore /* 13916b76705SSiddarth Gore * Enable RGMII delay on Tx and Rx for CPU port 14016b76705SSiddarth Gore * Ref: sec 4.7.2 of chip datasheet 14116b76705SSiddarth Gore */ 14216b76705SSiddarth Gore miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2); 14316b76705SSiddarth Gore miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, ®); 14416b76705SSiddarth Gore reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL); 14516b76705SSiddarth Gore miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg); 14616b76705SSiddarth Gore miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0); 14716b76705SSiddarth Gore 14816b76705SSiddarth Gore /* reset the phy */ 149*3f786bb8SMahavir Jain miiphy_reset(name, devadr); 15016b76705SSiddarth Gore 15116b76705SSiddarth Gore printf("88E1121 Initialized on %s\n", name); 15216b76705SSiddarth Gore } 15316b76705SSiddarth Gore 15416b76705SSiddarth Gore void reset_phy(void) 15516b76705SSiddarth Gore { 15616b76705SSiddarth Gore /* configure and initialize both PHY's */ 15716b76705SSiddarth Gore mv_phy_88e1121_init("egiga0"); 15816b76705SSiddarth Gore mv_phy_88e1121_init("egiga1"); 15916b76705SSiddarth Gore } 16016b76705SSiddarth Gore #endif /* CONFIG_RESET_PHY_R */ 161