1 /* 2 * (C) Copyright 2011 3 * eInfochips Ltd. <www.einfochips.com> 4 * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com> 5 * 6 * Based on Aspenite: 7 * (C) Copyright 2010 8 * Marvell Semiconductor <www.marvell.com> 9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 10 * Contributor: Mahavir Jain <mjain@marvell.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 28 * MA 02110-1301 USA 29 */ 30 31 #include <common.h> 32 #include <mvmfp.h> 33 #include <asm/arch/cpu.h> 34 #include <asm/arch/mfp.h> 35 #include <asm/arch/armada100.h> 36 #include <asm/gpio.h> 37 #include <miiphy.h> 38 39 #ifdef CONFIG_ARMADA100_FEC 40 #include <net.h> 41 #include <netdev.h> 42 #endif /* CONFIG_ARMADA100_FEC */ 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 int board_early_init_f(void) 47 { 48 u32 mfp_cfg[] = { 49 /* I2C */ 50 MFP105_CI2C_SDA, 51 MFP106_CI2C_SCL, 52 53 /* Enable Console on UART3 */ 54 MFPO8_UART3_TXD, 55 MFPO9_UART3_RXD, 56 57 /* Ethernet PHY Interface */ 58 MFP086_ETH_TXCLK, 59 MFP087_ETH_TXEN, 60 MFP088_ETH_TXDQ3, 61 MFP089_ETH_TXDQ2, 62 MFP090_ETH_TXDQ1, 63 MFP091_ETH_TXDQ0, 64 MFP092_ETH_CRS, 65 MFP093_ETH_COL, 66 MFP094_ETH_RXCLK, 67 MFP095_ETH_RXER, 68 MFP096_ETH_RXDQ3, 69 MFP097_ETH_RXDQ2, 70 MFP098_ETH_RXDQ1, 71 MFP099_ETH_RXDQ0, 72 MFP100_ETH_MDC, 73 MFP101_ETH_MDIO, 74 MFP103_ETH_RXDV, 75 76 /* SSP2 */ 77 MFP107_SSP2_RXD, 78 MFP108_SSP2_TXD, 79 MFP110_SSP2_CS, 80 MFP111_SSP2_CLK, 81 82 MFP_EOC /*End of configuration*/ 83 }; 84 /* configure MFP's */ 85 mfp_config(mfp_cfg); 86 return 0; 87 } 88 89 int board_init(void) 90 { 91 struct armd1apb2_registers *apb2_regs = 92 (struct armd1apb2_registers *)ARMD1_APBC2_BASE; 93 94 /* arch number of Board */ 95 gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD; 96 /* adress of boot parameters */ 97 gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; 98 /* Assert PHY_RST# */ 99 gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW); 100 udelay(10); 101 /* Deassert PHY_RST# */ 102 gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH); 103 104 /* Enable SSP2 clock */ 105 writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst); 106 return 0; 107 } 108 109 #ifdef CONFIG_ARMADA100_FEC 110 int board_eth_init(bd_t *bis) 111 { 112 struct armd1apmu_registers *apmu_regs = 113 (struct armd1apmu_registers *)ARMD1_APMU_BASE; 114 115 /* Enable clock of ethernet controller */ 116 writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc); 117 118 return armada100_fec_register(ARMD1_FEC_BASE); 119 } 120 121 #ifdef CONFIG_RESET_PHY_R 122 /* Configure and initialize PHY chip 88E3015 */ 123 void reset_phy(void) 124 { 125 u16 phy_adr; 126 const char *name = "armd-fec0"; 127 128 if (miiphy_set_current_dev(name)) 129 return; 130 131 /* command to read PHY dev address */ 132 if (miiphy_read(name, 0xff, 0xff, &phy_adr)) { 133 printf("Err..%s could not read PHY dev address\n", __func__); 134 return; 135 } 136 137 /* Set Ethernet LED in TX blink mode */ 138 miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00); 139 miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL); 140 141 /* reset the phy */ 142 miiphy_reset(name, phy_adr); 143 debug("88E3015 Initialized on %s\n", name); 144 } 145 #endif /* CONFIG_RESET_PHY_R */ 146 #endif /* CONFIG_ARMADA100_FEC */ 147