1 /* 2 * (C) Copyright 2011 3 * eInfochips Ltd. <www.einfochips.com> 4 * Written-by: Ajay Bhargav <contact@8051projects.net> 5 * 6 * Based on Aspenite: 7 * (C) Copyright 2010 8 * Marvell Semiconductor <www.marvell.com> 9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 10 * Contributor: Mahavir Jain <mjain@marvell.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <mvmfp.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/mfp.h> 19 #include <asm/arch/armada100.h> 20 #include <asm/gpio.h> 21 #include <miiphy.h> 22 #include <asm/mach-types.h> 23 24 #ifdef CONFIG_ARMADA100_FEC 25 #include <net.h> 26 #include <netdev.h> 27 #endif /* CONFIG_ARMADA100_FEC */ 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 int board_early_init_f(void) 32 { 33 u32 mfp_cfg[] = { 34 /* I2C */ 35 MFP105_CI2C_SDA, 36 MFP106_CI2C_SCL, 37 38 /* Enable Console on UART3 */ 39 MFPO8_UART3_TXD, 40 MFPO9_UART3_RXD, 41 42 /* Ethernet PHY Interface */ 43 MFP086_ETH_TXCLK, 44 MFP087_ETH_TXEN, 45 MFP088_ETH_TXDQ3, 46 MFP089_ETH_TXDQ2, 47 MFP090_ETH_TXDQ1, 48 MFP091_ETH_TXDQ0, 49 MFP092_ETH_CRS, 50 MFP093_ETH_COL, 51 MFP094_ETH_RXCLK, 52 MFP095_ETH_RXER, 53 MFP096_ETH_RXDQ3, 54 MFP097_ETH_RXDQ2, 55 MFP098_ETH_RXDQ1, 56 MFP099_ETH_RXDQ0, 57 MFP100_ETH_MDC, 58 MFP101_ETH_MDIO, 59 MFP103_ETH_RXDV, 60 61 /* SSP2 */ 62 MFP107_SSP2_RXD, 63 MFP108_SSP2_TXD, 64 MFP110_SSP2_CS, 65 MFP111_SSP2_CLK, 66 67 MFP_EOC /*End of configuration*/ 68 }; 69 /* configure MFP's */ 70 mfp_config(mfp_cfg); 71 return 0; 72 } 73 74 int board_init(void) 75 { 76 struct armd1apb2_registers *apb2_regs = 77 (struct armd1apb2_registers *)ARMD1_APBC2_BASE; 78 79 /* arch number of Board */ 80 gd->bd->bi_arch_number = MACH_TYPE_GPLUGD; 81 /* adress of boot parameters */ 82 gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; 83 /* Assert PHY_RST# */ 84 gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW); 85 udelay(10); 86 /* Deassert PHY_RST# */ 87 gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH); 88 89 /* Enable SSP2 clock */ 90 writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst); 91 return 0; 92 } 93 94 #ifdef CONFIG_ARMADA100_FEC 95 int board_eth_init(bd_t *bis) 96 { 97 struct armd1apmu_registers *apmu_regs = 98 (struct armd1apmu_registers *)ARMD1_APMU_BASE; 99 100 /* Enable clock of ethernet controller */ 101 writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc); 102 103 return armada100_fec_register(ARMD1_FEC_BASE); 104 } 105 106 #ifdef CONFIG_RESET_PHY_R 107 /* Configure and initialize PHY chip 88E3015 */ 108 void reset_phy(void) 109 { 110 u16 phy_adr; 111 const char *name = "armd-fec0"; 112 113 if (miiphy_set_current_dev(name)) 114 return; 115 116 /* command to read PHY dev address */ 117 if (miiphy_read(name, 0xff, 0xff, &phy_adr)) { 118 printf("Err..%s could not read PHY dev address\n", __func__); 119 return; 120 } 121 122 /* Set Ethernet LED in TX blink mode */ 123 miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00); 124 miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL); 125 126 /* reset the phy */ 127 miiphy_reset(name, phy_adr); 128 debug("88E3015 Initialized on %s\n", name); 129 } 130 #endif /* CONFIG_RESET_PHY_R */ 131 #endif /* CONFIG_ARMADA100_FEC */ 132