1#
2# (C) Copyright 2011
3# Jason Cooper <u-boot@lakedaemon.net>
4#
5# Based on work by:
6# Marvell Semiconductor <www.marvell.com>
7# Written-by: Siddarth Gore <gores@marvell.com>
8#
9# See file CREDITS for list of people who contributed to this
10# project.
11#
12# This program is free software; you can redistribute it and/or
13# modify it under the terms of the GNU General Public License as
14# published by the Free Software Foundation; either version 2 of
15# the License, or (at your option) any later version.
16#
17# This program is distributed in the hope that it will be useful,
18# but WITHOUT ANY WARRANTY; without even the implied warranty of
19# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20# GNU General Public License for more details.
21#
22# You should have received a copy of the GNU General Public License
23# along with this program; if not, write to the Free Software
24# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
25# MA 02110-1301 USA
26#
27# Refer doc/README.kwbimage for more details about how-to configure
28# and create kirkwood boot image
29#
30
31# Boot Media configurations
32BOOT_FROM	spi
33
34# SOC registers configuration using bootrom header extension
35# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
36
37# Configure RGMII-0/1 interface pad voltage to 1.8V
38DATA 0xFFD100e0 0x1b1b9b9b
39
40#Dram initalization for SINGLE x16 CL=5 @ 400MHz
41DATA 0xFFD01400 0x43000c30	# DDR Configuration register
42# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
43# bit23-14: zero
44# bit24: 1= enable exit self refresh mode on DDR access
45# bit25: 1 required
46# bit29-26: zero
47# bit31-30: 01
48
49DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
50# bit 4:    0=addr/cmd in smame cycle
51# bit 5:    0=clk is driven during self refresh, we don't care for APX
52# bit 6:    0=use recommended falling edge of clk for addr/cmd
53# bit14:    0=input buffer always powered up
54# bit18:    1=cpu lock transaction enabled
55# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
56# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
57# bit30-28: 3 required
58# bit31:    0=no additional STARTBURST delay
59
60DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
61# bit3-0:   TRAS lsbs
62# bit7-4:   TRCD
63# bit11- 8: TRP
64# bit15-12: TWR
65# bit19-16: TWTR
66# bit20:    TRAS msb
67# bit23-21: 0x0
68# bit27-24: TRRD
69# bit31-28: TRTP
70
71DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
72# bit6-0:   TRFC
73# bit8-7:   TR2R
74# bit10-9:  TR2W
75# bit12-11: TW2W
76# bit31-13: zero required
77
78DATA 0xFFD01410 0x000000cc	#  DDR Address Control
79# bit1-0:   01, Cs0width=x8
80# bit3-2:   10, Cs0size=1Gb
81# bit5-4:   01, Cs1width=x8
82# bit7-6:   10, Cs1size=1Gb
83# bit9-8:   00, Cs2width=nonexistent
84# bit11-10: 00, Cs2size =nonexistent
85# bit13-12: 00, Cs3width=nonexistent
86# bit15-14: 00, Cs3size =nonexistent
87# bit16:    0,  Cs0AddrSel
88# bit17:    0,  Cs1AddrSel
89# bit18:    0,  Cs2AddrSel
90# bit19:    0,  Cs3AddrSel
91# bit31-20: 0 required
92
93DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
94# bit0:    0,  OpenPage enabled
95# bit31-1: 0 required
96
97DATA 0xFFD01418 0x00000000	#  DDR Operation
98# bit3-0:   0x0, DDR cmd
99# bit31-4:  0 required
100
101DATA 0xFFD0141C 0x00000C52	#  DDR Mode
102# bit2-0:   2, BurstLen=2 required
103# bit3:     0, BurstType=0 required
104# bit6-4:   4, CL=5
105# bit7:     0, TestMode=0 normal
106# bit8:     0, DLL reset=0 normal
107# bit11-9:  6, auto-precharge write recovery ????????????
108# bit12:    0, PD must be zero
109# bit31-13: 0 required
110
111DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
112# bit0:    0,  DDR DLL enabled
113# bit1:    0,  DDR drive strenght normal
114# bit2:    0,  DDR ODT control lsd (disabled)
115# bit5-3:  000, required
116# bit6:    1,  DDR ODT control msb, (disabled)
117# bit9-7:  000, required
118# bit10:   0,  differential DQS enabled
119# bit11:   0, required
120# bit12:   0, DDR output buffer enabled
121# bit31-13: 0 required
122
123DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
124# bit2-0:  111, required
125# bit3  :  1  , MBUS Burst Chop disabled
126# bit6-4:  111, required
127# bit7  :  0
128# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
129# bit9  :  0  , no half clock cycle addition to dataout
130# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
131# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
132# bit15-12: 1111 required
133# bit31-16: 0    required
134
135DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
136DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
137
138DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
139DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
140# bit0:    1,  Window enabled
141# bit1:    0,  Write Protect disabled
142# bit3-2:  00, CS0 hit selected
143# bit23-4: ones, required
144# bit31-24: 0x0F, Size (i.e. 256MB)
145
146DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
147DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
148
149DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
150DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
151
152DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
153DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
154# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
155# bit3-2:  01, ODT1 active NEVER!
156# bit31-4: zero, required
157
158DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
159DATA 0xFFD01480 0x00000001	# DDR Initialization Control
160#bit0=1, enable DDR init upon this register write
161
162# End of Header extension
163DATA 0x0 0x0
164