1#
2# (C) Copyright 2011
3# Jason Cooper <u-boot@lakedaemon.net>
4#
5# Based on work by:
6# Marvell Semiconductor <www.marvell.com>
7# Written-by: Siddarth Gore <gores@marvell.com>
8#
9# SPDX-License-Identifier:	GPL-2.0+
10#
11# Refer doc/README.kwbimage for more details about how-to configure
12# and create kirkwood boot image
13#
14
15# Boot Media configurations
16BOOT_FROM	spi
17
18# SOC registers configuration using bootrom header extension
19# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
20
21# Configure RGMII-0/1 interface pad voltage to 1.8V
22DATA 0xFFD100e0 0x1b1b9b9b
23
24#Dram initalization for SINGLE x16 CL=5 @ 400MHz
25DATA 0xFFD01400 0x43000c30	# DDR Configuration register
26# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
27# bit23-14: zero
28# bit24: 1= enable exit self refresh mode on DDR access
29# bit25: 1 required
30# bit29-26: zero
31# bit31-30: 01
32
33DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
34# bit 4:    0=addr/cmd in smame cycle
35# bit 5:    0=clk is driven during self refresh, we don't care for APX
36# bit 6:    0=use recommended falling edge of clk for addr/cmd
37# bit14:    0=input buffer always powered up
38# bit18:    1=cpu lock transaction enabled
39# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
40# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
41# bit30-28: 3 required
42# bit31:    0=no additional STARTBURST delay
43
44DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
45# bit3-0:   TRAS lsbs
46# bit7-4:   TRCD
47# bit11- 8: TRP
48# bit15-12: TWR
49# bit19-16: TWTR
50# bit20:    TRAS msb
51# bit23-21: 0x0
52# bit27-24: TRRD
53# bit31-28: TRTP
54
55DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
56# bit6-0:   TRFC
57# bit8-7:   TR2R
58# bit10-9:  TR2W
59# bit12-11: TW2W
60# bit31-13: zero required
61
62DATA 0xFFD01410 0x000000cc	#  DDR Address Control
63# bit1-0:   01, Cs0width=x8
64# bit3-2:   10, Cs0size=1Gb
65# bit5-4:   01, Cs1width=x8
66# bit7-6:   10, Cs1size=1Gb
67# bit9-8:   00, Cs2width=nonexistent
68# bit11-10: 00, Cs2size =nonexistent
69# bit13-12: 00, Cs3width=nonexistent
70# bit15-14: 00, Cs3size =nonexistent
71# bit16:    0,  Cs0AddrSel
72# bit17:    0,  Cs1AddrSel
73# bit18:    0,  Cs2AddrSel
74# bit19:    0,  Cs3AddrSel
75# bit31-20: 0 required
76
77DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
78# bit0:    0,  OpenPage enabled
79# bit31-1: 0 required
80
81DATA 0xFFD01418 0x00000000	#  DDR Operation
82# bit3-0:   0x0, DDR cmd
83# bit31-4:  0 required
84
85DATA 0xFFD0141C 0x00000C52	#  DDR Mode
86# bit2-0:   2, BurstLen=2 required
87# bit3:     0, BurstType=0 required
88# bit6-4:   4, CL=5
89# bit7:     0, TestMode=0 normal
90# bit8:     0, DLL reset=0 normal
91# bit11-9:  6, auto-precharge write recovery ????????????
92# bit12:    0, PD must be zero
93# bit31-13: 0 required
94
95DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
96# bit0:    0,  DDR DLL enabled
97# bit1:    0,  DDR drive strenght normal
98# bit2:    0,  DDR ODT control lsd (disabled)
99# bit5-3:  000, required
100# bit6:    1,  DDR ODT control msb, (disabled)
101# bit9-7:  000, required
102# bit10:   0,  differential DQS enabled
103# bit11:   0, required
104# bit12:   0, DDR output buffer enabled
105# bit31-13: 0 required
106
107DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
108# bit2-0:  111, required
109# bit3  :  1  , MBUS Burst Chop disabled
110# bit6-4:  111, required
111# bit7  :  0
112# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
113# bit9  :  0  , no half clock cycle addition to dataout
114# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
115# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
116# bit15-12: 1111 required
117# bit31-16: 0    required
118
119DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
120DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
121
122DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
123DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
124# bit0:    1,  Window enabled
125# bit1:    0,  Write Protect disabled
126# bit3-2:  00, CS0 hit selected
127# bit23-4: ones, required
128# bit31-24: 0x0F, Size (i.e. 256MB)
129
130DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
131DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
132
133DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
134DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
135
136DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
137DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
138# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
139# bit3-2:  01, ODT1 active NEVER!
140# bit31-4: zero, required
141
142DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
143DATA 0xFFD01480 0x00000001	# DDR Initialization Control
144#bit0=1, enable DDR init upon this register write
145
146# End of Header extension
147DATA 0x0 0x0
148