1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2011
4  * Jason Cooper <u-boot@lakedaemon.net>
5  *
6  * Based on work by:
7  * Marvell Semiconductor <www.marvell.com>
8  * Written-by: Siddarth Gore <gores@marvell.com>
9  */
10 
11 #include <common.h>
12 #include <miiphy.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15 #include <asm/arch/mpp.h>
16 #include "dreamplug.h"
17 
18 DECLARE_GLOBAL_DATA_PTR;
19 
20 int board_early_init_f(void)
21 {
22 	/*
23 	 * default gpio configuration
24 	 * There are maximum 64 gpios controlled through 2 sets of registers
25 	 * the  below configuration configures mainly initial LED status
26 	 */
27 	mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
28 			  DREAMPLUG_OE_VAL_HIGH,
29 			  DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
30 
31 	/* Multi-Purpose Pins Functionality configuration */
32 	static const u32 kwmpp_config[] = {
33 		MPP0_SPI_SCn,		/* SPI Flash */
34 		MPP1_SPI_MOSI,
35 		MPP2_SPI_SCK,
36 		MPP3_SPI_MISO,
37 		MPP4_NF_IO6,
38 		MPP5_NF_IO7,
39 		MPP6_SYSRST_OUTn,
40 		MPP7_GPO,
41 		MPP8_TW_SDA,
42 		MPP9_TW_SCK,
43 		MPP10_UART0_TXD,	/* Serial */
44 		MPP11_UART0_RXD,
45 		MPP12_SD_CLK,		/* SDIO Slot */
46 		MPP13_SD_CMD,
47 		MPP14_SD_D0,
48 		MPP15_SD_D1,
49 		MPP16_SD_D2,
50 		MPP17_SD_D3,
51 		MPP18_NF_IO0,
52 		MPP19_NF_IO1,
53 		MPP20_GE1_0,		/* Gigabit Ethernet */
54 		MPP21_GE1_1,
55 		MPP22_GE1_2,
56 		MPP23_GE1_3,
57 		MPP24_GE1_4,
58 		MPP25_GE1_5,
59 		MPP26_GE1_6,
60 		MPP27_GE1_7,
61 		MPP28_GE1_8,
62 		MPP29_GE1_9,
63 		MPP30_GE1_10,
64 		MPP31_GE1_11,
65 		MPP32_GE1_12,
66 		MPP33_GE1_13,
67 		MPP34_GE1_14,
68 		MPP35_GE1_15,
69 		MPP36_GPIO,		/* 7 external GPIO pins (36 - 45) */
70 		MPP37_GPIO,
71 		MPP38_GPIO,
72 		MPP39_GPIO,
73 		MPP40_TDM_SPI_SCK,
74 		MPP41_TDM_SPI_MISO,
75 		MPP42_TDM_SPI_MOSI,
76 		MPP43_GPIO,
77 		MPP44_GPIO,
78 		MPP45_GPIO,
79 		MPP46_GPIO,
80 		MPP47_GPIO,		/* Bluetooth LED */
81 		MPP48_GPIO,		/* Wifi LED */
82 		MPP49_GPIO,		/* Wifi AP LED */
83 		0
84 	};
85 	kirkwood_mpp_conf(kwmpp_config, NULL);
86 	return 0;
87 }
88 
89 int board_init(void)
90 {
91 	/* adress of boot parameters */
92 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
93 
94 	return 0;
95 }
96 
97 #ifdef CONFIG_RESET_PHY_R
98 void mv_phy_88e1116_init(char *name)
99 {
100 	u16 reg;
101 	u16 devadr;
102 
103 	if (miiphy_set_current_dev(name))
104 		return;
105 
106 	/* command to read PHY dev address */
107 	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
108 		printf("Err..%s could not read PHY dev address\n",
109 			__func__);
110 		return;
111 	}
112 
113 	/*
114 	 * Enable RGMII delay on Tx and Rx for CPU port
115 	 * Ref: sec 4.7.2 of chip datasheet
116 	 */
117 	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
118 	miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
119 	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
120 	miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
121 	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
122 
123 	/* reset the phy */
124 	miiphy_reset(name, devadr);
125 
126 	printf("88E1116 Initialized on %s\n", name);
127 }
128 
129 void reset_phy(void)
130 {
131 	/* configure and initialize both PHY's */
132 	mv_phy_88e1116_init("egiga0");
133 	mv_phy_88e1116_init("egiga1");
134 }
135 #endif /* CONFIG_RESET_PHY_R */
136