1 /* 2 * (C) Copyright 2011 3 * Jason Cooper <u-boot@lakedaemon.net> 4 * 5 * Based on work by: 6 * Marvell Semiconductor <www.marvell.com> 7 * Written-by: Siddarth Gore <gores@marvell.com> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 25 * MA 02110-1301 USA 26 */ 27 28 #include <common.h> 29 #include <miiphy.h> 30 #include <asm/arch/kirkwood.h> 31 #include <asm/arch/mpp.h> 32 #include "dreamplug.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 int board_early_init_f(void) 37 { 38 /* 39 * default gpio configuration 40 * There are maximum 64 gpios controlled through 2 sets of registers 41 * the below configuration configures mainly initial LED status 42 */ 43 kw_config_gpio(DREAMPLUG_OE_VAL_LOW, 44 DREAMPLUG_OE_VAL_HIGH, 45 DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH); 46 47 /* Multi-Purpose Pins Functionality configuration */ 48 u32 kwmpp_config[] = { 49 MPP0_SPI_SCn, /* SPI Flash */ 50 MPP1_SPI_MOSI, 51 MPP2_SPI_SCK, 52 MPP3_SPI_MISO, 53 MPP4_NF_IO6, 54 MPP5_NF_IO7, 55 MPP6_SYSRST_OUTn, 56 MPP7_GPO, 57 MPP8_TW_SDA, 58 MPP9_TW_SCK, 59 MPP10_UART0_TXD, /* Serial */ 60 MPP11_UART0_RXD, 61 MPP12_SD_CLK, /* SDIO Slot */ 62 MPP13_SD_CMD, 63 MPP14_SD_D0, 64 MPP15_SD_D1, 65 MPP16_SD_D2, 66 MPP17_SD_D3, 67 MPP18_NF_IO0, 68 MPP19_NF_IO1, 69 MPP20_GE1_0, /* Gigabit Ethernet */ 70 MPP21_GE1_1, 71 MPP22_GE1_2, 72 MPP23_GE1_3, 73 MPP24_GE1_4, 74 MPP25_GE1_5, 75 MPP26_GE1_6, 76 MPP27_GE1_7, 77 MPP28_GE1_8, 78 MPP29_GE1_9, 79 MPP30_GE1_10, 80 MPP31_GE1_11, 81 MPP32_GE1_12, 82 MPP33_GE1_13, 83 MPP34_GE1_14, 84 MPP35_GE1_15, 85 MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */ 86 MPP37_GPIO, 87 MPP38_GPIO, 88 MPP39_GPIO, 89 MPP40_TDM_SPI_SCK, 90 MPP41_TDM_SPI_MISO, 91 MPP42_TDM_SPI_MOSI, 92 MPP43_GPIO, 93 MPP44_GPIO, 94 MPP45_GPIO, 95 MPP46_GPIO, 96 MPP47_GPIO, /* Bluetooth LED */ 97 MPP48_GPIO, /* Wifi LED */ 98 MPP49_GPIO, /* Wifi AP LED */ 99 0 100 }; 101 kirkwood_mpp_conf(kwmpp_config); 102 return 0; 103 } 104 105 int board_init(void) 106 { 107 /* adress of boot parameters */ 108 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 109 110 return 0; 111 } 112 113 #ifdef CONFIG_RESET_PHY_R 114 void mv_phy_88e1116_init(char *name) 115 { 116 u16 reg; 117 u16 devadr; 118 119 if (miiphy_set_current_dev(name)) 120 return; 121 122 /* command to read PHY dev address */ 123 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { 124 printf("Err..%s could not read PHY dev address\n", 125 __func__); 126 return; 127 } 128 129 /* 130 * Enable RGMII delay on Tx and Rx for CPU port 131 * Ref: sec 4.7.2 of chip datasheet 132 */ 133 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); 134 miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®); 135 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); 136 miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg); 137 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); 138 139 /* reset the phy */ 140 miiphy_reset(name, devadr); 141 142 printf("88E1116 Initialized on %s\n", name); 143 } 144 145 void reset_phy(void) 146 { 147 /* configure and initialize both PHY's */ 148 mv_phy_88e1116_init("egiga0"); 149 mv_phy_88e1116_init("egiga1"); 150 } 151 #endif /* CONFIG_RESET_PHY_R */ 152