1 /*
2  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <miiphy.h>
9 #include <asm/io.h>
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/soc.h>
12 
13 DECLARE_GLOBAL_DATA_PTR;
14 
15 #define BIT(nr)				(1UL << (nr))
16 
17 #define ETH_PHY_CTRL_REG		0
18 #define ETH_PHY_CTRL_POWER_DOWN_BIT	11
19 #define ETH_PHY_CTRL_POWER_DOWN_MASK	(1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
20 
21 /*
22  * Those values and defines are taken from the Marvell U-Boot version
23  * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
24  * "RD-AXP-GP rev 1.0".
25  *
26  * GPPs
27  * MPP#		NAME			IN/OUT
28  * ----------------------------------------------
29  * 21		SW_Reset_		OUT
30  * 25		Phy_Int#		IN
31  * 28		SDI_WP			IN
32  * 29		SDI_Status		IN
33  * 54-61	On GPP Connector	?
34  * 62		Switch Interrupt	IN
35  * 63-65	Reserved from SW Board	?
36  * 66		SW_BRD connected	IN
37  */
38 #define RD_78460_GP_GPP_OUT_ENA_LOW	(~(BIT(21) | BIT(20)))
39 #define RD_78460_GP_GPP_OUT_ENA_MID	(~(BIT(26) | BIT(27)))
40 #define RD_78460_GP_GPP_OUT_ENA_HIGH	(~(0x0))
41 
42 #define RD_78460_GP_GPP_OUT_VAL_LOW	(BIT(21) | BIT(20))
43 #define RD_78460_GP_GPP_OUT_VAL_MID	(BIT(26) | BIT(27))
44 #define RD_78460_GP_GPP_OUT_VAL_HIGH	0x0
45 
46 int board_early_init_f(void)
47 {
48 	/* Configure MPP */
49 	writel(0x00000000, MVEBU_MPP_BASE + 0x00);
50 	writel(0x00000000, MVEBU_MPP_BASE + 0x04);
51 	writel(0x33000000, MVEBU_MPP_BASE + 0x08);
52 	writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
53 	writel(0x11111111, MVEBU_MPP_BASE + 0x10);
54 	writel(0x00221100, MVEBU_MPP_BASE + 0x14);
55 	writel(0x00000003, MVEBU_MPP_BASE + 0x18);
56 	writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
57 	writel(0x00000000, MVEBU_MPP_BASE + 0x20);
58 
59 	/* Configure GPIO */
60 	writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
61 	writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
62 	writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
63 	writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
64 	writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
65 	writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
66 
67 	return 0;
68 }
69 
70 int board_init(void)
71 {
72 	/* adress of boot parameters */
73 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
74 
75 	return 0;
76 }
77 
78 int checkboard(void)
79 {
80 	puts("Board: Marvell DB-MV784MP-GP\n");
81 
82 	return 0;
83 }
84 
85 #ifdef CONFIG_RESET_PHY_R
86 /* Configure and enable MV88E1545 PHY */
87 void reset_phy(void)
88 {
89 	u16 devadr = CONFIG_PHY_BASE_ADDR;
90 	char *name = "neta0";
91 	u16 reg;
92 
93 	if (miiphy_set_current_dev(name))
94 		return;
95 
96 	/* Enable QSGMII AN */
97 	/* Set page to 4 */
98 	miiphy_write(name, devadr, 0x16, 4);
99 	/* Enable AN */
100 	miiphy_write(name, devadr, 0x0, 0x1140);
101 	/* Set page to 0 */
102 	miiphy_write(name, devadr, 0x16, 0);
103 
104 	/* Phy C_ANEG */
105 	miiphy_read(name, devadr, 0x4, &reg);
106 	reg |= 0x1E0;
107 	miiphy_write(name, devadr, 0x4, reg);
108 
109 	/* Soft-Reset */
110 	miiphy_write(name, devadr, 22, 0x0000);
111 	miiphy_write(name, devadr, 0, 0x9140);
112 
113 	/* Power up the phy */
114 	miiphy_read(name, devadr, ETH_PHY_CTRL_REG, &reg);
115 	reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
116 	miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg);
117 
118 	printf("88E1545 Initialized on %s\n", name);
119 }
120 #endif /* CONFIG_RESET_PHY_R */
121