1 /*
2  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <miiphy.h>
9 #include <netdev.h>
10 #include <asm/io.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13 
14 DECLARE_GLOBAL_DATA_PTR;
15 
16 #define ETH_PHY_CTRL_REG		0
17 #define ETH_PHY_CTRL_POWER_DOWN_BIT	11
18 #define ETH_PHY_CTRL_POWER_DOWN_MASK	(1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
19 
20 /*
21  * Those values and defines are taken from the Marvell U-Boot version
22  * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
23  * "RD-AXP-GP rev 1.0".
24  *
25  * GPPs
26  * MPP#		NAME			IN/OUT
27  * ----------------------------------------------
28  * 21		SW_Reset_		OUT
29  * 25		Phy_Int#		IN
30  * 28		SDI_WP			IN
31  * 29		SDI_Status		IN
32  * 54-61	On GPP Connector	?
33  * 62		Switch Interrupt	IN
34  * 63-65	Reserved from SW Board	?
35  * 66		SW_BRD connected	IN
36  */
37 #define RD_78460_GP_GPP_OUT_ENA_LOW	(~(BIT(21) | BIT(20)))
38 #define RD_78460_GP_GPP_OUT_ENA_MID	(~(BIT(26) | BIT(27)))
39 #define RD_78460_GP_GPP_OUT_ENA_HIGH	(~(0x0))
40 
41 #define RD_78460_GP_GPP_OUT_VAL_LOW	(BIT(21) | BIT(20))
42 #define RD_78460_GP_GPP_OUT_VAL_MID	(BIT(26) | BIT(27))
43 #define RD_78460_GP_GPP_OUT_VAL_HIGH	0x0
44 
45 int board_early_init_f(void)
46 {
47 	/* Configure MPP */
48 	writel(0x00000000, MVEBU_MPP_BASE + 0x00);
49 	writel(0x00000000, MVEBU_MPP_BASE + 0x04);
50 	writel(0x33000000, MVEBU_MPP_BASE + 0x08);
51 	writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
52 	writel(0x11111111, MVEBU_MPP_BASE + 0x10);
53 	writel(0x00221100, MVEBU_MPP_BASE + 0x14);
54 	writel(0x00000003, MVEBU_MPP_BASE + 0x18);
55 	writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
56 	writel(0x00000000, MVEBU_MPP_BASE + 0x20);
57 
58 	/* Configure GPIO */
59 	writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
60 	writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
61 	writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
62 	writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
63 	writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
64 	writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
65 
66 	return 0;
67 }
68 
69 int board_init(void)
70 {
71 	/* adress of boot parameters */
72 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
73 
74 	return 0;
75 }
76 
77 int checkboard(void)
78 {
79 	puts("Board: Marvell DB-MV784MP-GP\n");
80 
81 	return 0;
82 }
83 
84 int board_eth_init(bd_t *bis)
85 {
86 	cpu_eth_init(bis); /* Built in controller(s) come first */
87 	return pci_eth_init(bis);
88 }
89 
90 int board_phy_config(struct phy_device *phydev)
91 {
92 	u16 reg;
93 
94 	/* Enable QSGMII AN */
95 	/* Set page to 4 */
96 	phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
97 	/* Enable AN */
98 	phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
99 	/* Set page to 0 */
100 	phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
101 
102 	/* Phy C_ANEG */
103 	reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
104 	reg |= 0x1E0;
105 	phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
106 
107 	/* Soft-Reset */
108 	phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
109 	phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
110 
111 	/* Power up the phy */
112 	reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
113 	reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
114 	phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
115 
116 	printf("88E1545 Initialized\n");
117 	return 0;
118 }
119