1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <miiphy.h> 9 #include <asm/io.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/soc.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 #define ETH_PHY_CTRL_REG 0 16 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11 17 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) 18 19 /* 20 * Those values and defines are taken from the Marvell U-Boot version 21 * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka 22 * "RD-AXP-GP rev 1.0". 23 * 24 * GPPs 25 * MPP# NAME IN/OUT 26 * ---------------------------------------------- 27 * 21 SW_Reset_ OUT 28 * 25 Phy_Int# IN 29 * 28 SDI_WP IN 30 * 29 SDI_Status IN 31 * 54-61 On GPP Connector ? 32 * 62 Switch Interrupt IN 33 * 63-65 Reserved from SW Board ? 34 * 66 SW_BRD connected IN 35 */ 36 #define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20))) 37 #define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27))) 38 #define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0)) 39 40 #define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20)) 41 #define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27)) 42 #define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0 43 44 int board_early_init_f(void) 45 { 46 /* Configure MPP */ 47 writel(0x00000000, MVEBU_MPP_BASE + 0x00); 48 writel(0x00000000, MVEBU_MPP_BASE + 0x04); 49 writel(0x33000000, MVEBU_MPP_BASE + 0x08); 50 writel(0x11000000, MVEBU_MPP_BASE + 0x0c); 51 writel(0x11111111, MVEBU_MPP_BASE + 0x10); 52 writel(0x00221100, MVEBU_MPP_BASE + 0x14); 53 writel(0x00000003, MVEBU_MPP_BASE + 0x18); 54 writel(0x00000000, MVEBU_MPP_BASE + 0x1c); 55 writel(0x00000000, MVEBU_MPP_BASE + 0x20); 56 57 /* Configure GPIO */ 58 writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); 59 writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); 60 writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); 61 writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); 62 writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); 63 writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); 64 65 return 0; 66 } 67 68 int board_init(void) 69 { 70 /* adress of boot parameters */ 71 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 72 73 return 0; 74 } 75 76 int checkboard(void) 77 { 78 puts("Board: Marvell DB-MV784MP-GP\n"); 79 80 return 0; 81 } 82 83 #ifdef CONFIG_RESET_PHY_R 84 /* Configure and enable MV88E1545 PHY */ 85 void reset_phy(void) 86 { 87 u8 phy_addr[] = CONFIG_PHY_ADDR; 88 u16 devadr = phy_addr[0]; 89 char *name = "neta0"; 90 u16 reg; 91 92 if (miiphy_set_current_dev(name)) 93 return; 94 95 /* Enable QSGMII AN */ 96 /* Set page to 4 */ 97 miiphy_write(name, devadr, 0x16, 4); 98 /* Enable AN */ 99 miiphy_write(name, devadr, 0x0, 0x1140); 100 /* Set page to 0 */ 101 miiphy_write(name, devadr, 0x16, 0); 102 103 /* Phy C_ANEG */ 104 miiphy_read(name, devadr, 0x4, ®); 105 reg |= 0x1E0; 106 miiphy_write(name, devadr, 0x4, reg); 107 108 /* Soft-Reset */ 109 miiphy_write(name, devadr, 22, 0x0000); 110 miiphy_write(name, devadr, 0, 0x9140); 111 112 /* Power up the phy */ 113 miiphy_read(name, devadr, ETH_PHY_CTRL_REG, ®); 114 reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK); 115 miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg); 116 117 printf("88E1545 Initialized on %s\n", name); 118 } 119 #endif /* CONFIG_RESET_PHY_R */ 120