1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
4  */
5 
6 #include <common.h>
7 #include <i2c.h>
8 #include <miiphy.h>
9 #include <netdev.h>
10 #include <asm/io.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13 
14 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
15 #include <../serdes/a38x/high_speed_env_spec.h>
16 
17 DECLARE_GLOBAL_DATA_PTR;
18 
19 #define ETH_PHY_CTRL_REG		0
20 #define ETH_PHY_CTRL_POWER_DOWN_BIT	11
21 #define ETH_PHY_CTRL_POWER_DOWN_MASK	(1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
22 
23 /*
24  * Those values and defines are taken from the Marvell U-Boot version
25  * "u-boot-2013.01-2014_T3.0"
26  */
27 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW					\
28 	(~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |	\
29 	   BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |	\
30 	   BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
31 #define DB_GP_88F68XX_GPP_OUT_ENA_MID					\
32 	(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |	\
33 	   BIT(16) | BIT(17) | BIT(18)))
34 
35 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW	0x0
36 #define DB_GP_88F68XX_GPP_OUT_VAL_MID	0x0
37 #define DB_GP_88F68XX_GPP_POL_LOW	0x0
38 #define DB_GP_88F68XX_GPP_POL_MID	0x0
39 
40 /* IO expander on Marvell GP board includes e.g. fan enabling */
41 struct marvell_io_exp {
42 	u8 chip;
43 	u8 addr;
44 	u8 val;
45 };
46 
47 static struct marvell_io_exp io_exp[] = {
48 	{ 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
49 	{ 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
50 	{ 0x20, 2, 0x1D }, /* Output Data, register#0 */
51 	{ 0x20, 3, 0x18 }, /* Output Data, register#1 */
52 	{ 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits  */
53 	{ 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits  */
54 	{ 0x21, 2, 0x08 }, /* Output Data, register#0 */
55 	{ 0x21, 3, 0xC0 }  /* Output Data, register#1 */
56 };
57 
58 static struct serdes_map board_serdes_map[] = {
59 	{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
60 	{SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
61 	{SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
62 	{SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
63 	{SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
64 	{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
65 };
66 
67 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
68 {
69 	*serdes_map_array = board_serdes_map;
70 	*count = ARRAY_SIZE(board_serdes_map);
71 	return 0;
72 }
73 
74 /*
75  * Define the DDR layout / topology here in the board file. This will
76  * be used by the DDR3 init code in the SPL U-Boot version to configure
77  * the DDR3 controller.
78  */
79 static struct mv_ddr_topology_map board_topology_map = {
80 	DEBUG_LEVEL_ERROR,
81 	0x1, /* active interfaces */
82 	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
83 	{ { { {0x1, 0, 0, 0},
84 	      {0x1, 0, 0, 0},
85 	      {0x1, 0, 0, 0},
86 	      {0x1, 0, 0, 0},
87 	      {0x1, 0, 0, 0} },
88 	    SPEED_BIN_DDR_1866L,	/* speed_bin */
89 	    MV_DDR_DEV_WIDTH_8BIT,	/* memory_width */
90 	    MV_DDR_DIE_CAP_4GBIT,	/* mem_size */
91 	    MV_DDR_FREQ_800,		/* frequency */
92 	    0, 0,			/* cas_wl cas_l */
93 	    MV_DDR_TEMP_LOW,		/* temperature */
94 	    MV_DDR_TIM_DEFAULT} },	/* timing */
95 	BUS_MASK_32BIT,			/* Busses mask */
96 	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
97 	{ {0} },			/* raw spd data */
98 	{0}				/* timing parameters */
99 };
100 
101 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
102 {
103 	/* Return the board topology as defined in the board code */
104 	return &board_topology_map;
105 }
106 
107 int board_early_init_f(void)
108 {
109 	/* Configure MPP */
110 	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
111 	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
112 	writel(0x11244011, MVEBU_MPP_BASE + 0x08);
113 	writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
114 	writel(0x22200002, MVEBU_MPP_BASE + 0x10);
115 	writel(0x30042022, MVEBU_MPP_BASE + 0x14);
116 	writel(0x55550555, MVEBU_MPP_BASE + 0x18);
117 	writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
118 
119 	/* Set GPP Out value */
120 	writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
121 	writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
122 
123 	/* Set GPP Polarity */
124 	writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
125 	writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
126 
127 	/* Set GPP Out Enable */
128 	writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
129 	writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
130 
131 	return 0;
132 }
133 
134 int board_init(void)
135 {
136 	int i;
137 
138 	/* adress of boot parameters */
139 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
140 
141 	/* Init I2C IO expanders */
142 	for (i = 0; i < ARRAY_SIZE(io_exp); i++)
143 		i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
144 
145 	return 0;
146 }
147 
148 int checkboard(void)
149 {
150 	puts("Board: Marvell DB-88F6820-GP\n");
151 
152 	return 0;
153 }
154 
155 int board_eth_init(bd_t *bis)
156 {
157 	cpu_eth_init(bis); /* Built in controller(s) come first */
158 	return pci_eth_init(bis);
159 }
160