1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
4  */
5 
6 #include <common.h>
7 #include <i2c.h>
8 #include <miiphy.h>
9 #include <netdev.h>
10 #include <asm/io.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13 
14 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
15 #include <../serdes/a38x/high_speed_env_spec.h>
16 
17 DECLARE_GLOBAL_DATA_PTR;
18 
19 /*
20  * Those values and defines are taken from the Marvell U-Boot version
21  * "u-boot-2013.01-2014_T3.0"
22  */
23 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW					\
24 	(~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |	\
25 	   BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |	\
26 	   BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
27 #define DB_GP_88F68XX_GPP_OUT_ENA_MID					\
28 	(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |	\
29 	   BIT(16) | BIT(17) | BIT(18)))
30 
31 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW	0x0
32 #define DB_GP_88F68XX_GPP_OUT_VAL_MID	0x0
33 #define DB_GP_88F68XX_GPP_POL_LOW	0x0
34 #define DB_GP_88F68XX_GPP_POL_MID	0x0
35 
36 /* IO expander on Marvell GP board includes e.g. fan enabling */
37 struct marvell_io_exp {
38 	u8 chip;
39 	u8 addr;
40 	u8 val;
41 };
42 
43 static struct marvell_io_exp io_exp[] = {
44 	{ 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
45 	{ 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
46 	{ 0x20, 2, 0x1D }, /* Output Data, register#0 */
47 	{ 0x20, 3, 0x18 }, /* Output Data, register#1 */
48 	{ 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits  */
49 	{ 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits  */
50 	{ 0x21, 2, 0x08 }, /* Output Data, register#0 */
51 	{ 0x21, 3, 0xC0 }  /* Output Data, register#1 */
52 };
53 
54 static struct serdes_map board_serdes_map[] = {
55 	{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
56 	{SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
57 	{SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
58 	{SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
59 	{SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
60 	{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
61 };
62 
63 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
64 {
65 	*serdes_map_array = board_serdes_map;
66 	*count = ARRAY_SIZE(board_serdes_map);
67 	return 0;
68 }
69 
70 /*
71  * Define the DDR layout / topology here in the board file. This will
72  * be used by the DDR3 init code in the SPL U-Boot version to configure
73  * the DDR3 controller.
74  */
75 static struct mv_ddr_topology_map board_topology_map = {
76 	DEBUG_LEVEL_ERROR,
77 	0x1, /* active interfaces */
78 	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
79 	{ { { {0x1, 0, 0, 0},
80 	      {0x1, 0, 0, 0},
81 	      {0x1, 0, 0, 0},
82 	      {0x1, 0, 0, 0},
83 	      {0x1, 0, 0, 0} },
84 	    SPEED_BIN_DDR_1866L,	/* speed_bin */
85 	    MV_DDR_DEV_WIDTH_8BIT,	/* memory_width */
86 	    MV_DDR_DIE_CAP_4GBIT,	/* mem_size */
87 	    MV_DDR_FREQ_800,		/* frequency */
88 	    0, 0,			/* cas_wl cas_l */
89 	    MV_DDR_TEMP_LOW,		/* temperature */
90 	    MV_DDR_TIM_DEFAULT} },	/* timing */
91 	BUS_MASK_32BIT,			/* Busses mask */
92 	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
93 	{ {0} },			/* raw spd data */
94 	{0}				/* timing parameters */
95 };
96 
97 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
98 {
99 	/* Return the board topology as defined in the board code */
100 	return &board_topology_map;
101 }
102 
103 int board_early_init_f(void)
104 {
105 	/* Configure MPP */
106 	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
107 	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
108 	writel(0x11244011, MVEBU_MPP_BASE + 0x08);
109 	writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
110 	writel(0x22200002, MVEBU_MPP_BASE + 0x10);
111 	writel(0x30042022, MVEBU_MPP_BASE + 0x14);
112 	writel(0x55550555, MVEBU_MPP_BASE + 0x18);
113 	writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
114 
115 	/* Set GPP Out value */
116 	writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
117 	writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
118 
119 	/* Set GPP Polarity */
120 	writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
121 	writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
122 
123 	/* Set GPP Out Enable */
124 	writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
125 	writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
126 
127 	return 0;
128 }
129 
130 int board_init(void)
131 {
132 	int i;
133 
134 	/* adress of boot parameters */
135 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
136 
137 	/* Init I2C IO expanders */
138 	for (i = 0; i < ARRAY_SIZE(io_exp); i++)
139 		i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
140 
141 	return 0;
142 }
143 
144 int checkboard(void)
145 {
146 	puts("Board: Marvell DB-88F6820-GP\n");
147 
148 	return 0;
149 }
150 
151 int board_eth_init(bd_t *bis)
152 {
153 	cpu_eth_init(bis); /* Built in controller(s) come first */
154 	return pci_eth_init(bis);
155 }
156