1 /* 2 * Copyright (C) 2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <miiphy.h> 10 #include <asm/io.h> 11 #include <asm/arch/cpu.h> 12 #include <asm/arch/soc.h> 13 14 #include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h" 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 #define ETH_PHY_CTRL_REG 0 19 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11 20 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) 21 22 /* 23 * Those values and defines are taken from the Marvell U-Boot version 24 * "u-boot-2013.01-2014_T3.0" 25 */ 26 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW \ 27 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \ 28 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \ 29 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31))) 30 #define DB_GP_88F68XX_GPP_OUT_ENA_MID \ 31 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \ 32 BIT(16) | BIT(17) | BIT(18))) 33 34 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0 35 #define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0 36 #define DB_GP_88F68XX_GPP_POL_LOW 0x0 37 #define DB_GP_88F68XX_GPP_POL_MID 0x0 38 39 /* IO expander on Marvell GP board includes e.g. fan enabling */ 40 struct marvell_io_exp { 41 u8 chip; 42 u8 addr; 43 u8 val; 44 }; 45 46 static struct marvell_io_exp io_exp[] = { 47 { 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */ 48 { 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */ 49 { 0x20, 2, 0x1D }, /* Output Data, register#0 */ 50 { 0x20, 3, 0x18 }, /* Output Data, register#1 */ 51 { 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */ 52 { 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */ 53 { 0x21, 2, 0x08 }, /* Output Data, register#0 */ 54 { 0x21, 3, 0xC0 } /* Output Data, register#1 */ 55 }; 56 57 /* 58 * Define the DDR layout / topology here in the board file. This will 59 * be used by the DDR3 init code in the SPL U-Boot version to configure 60 * the DDR3 controller. 61 */ 62 static struct hws_topology_map board_topology_map = { 63 0x1, /* active interfaces */ 64 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ 65 { { { {0x1, 0, 0, 0}, 66 {0x1, 0, 0, 0}, 67 {0x1, 0, 0, 0}, 68 {0x1, 0, 0, 0}, 69 {0x1, 0, 0, 0} }, 70 SPEED_BIN_DDR_1866L, /* speed_bin */ 71 BUS_WIDTH_8, /* memory_width */ 72 MEM_4G, /* mem_size */ 73 DDR_FREQ_800, /* frequency */ 74 0, 0, /* cas_l cas_wl */ 75 HWS_TEMP_LOW} }, /* temperature */ 76 5, /* Num Of Bus Per Interface*/ 77 BUS_MASK_32BIT /* Busses mask */ 78 }; 79 80 struct hws_topology_map *ddr3_get_topology_map(void) 81 { 82 /* Return the board topology as defined in the board code */ 83 return &board_topology_map; 84 } 85 86 int board_early_init_f(void) 87 { 88 /* Configure MPP */ 89 writel(0x11111111, MVEBU_MPP_BASE + 0x00); 90 writel(0x11111111, MVEBU_MPP_BASE + 0x04); 91 writel(0x11244011, MVEBU_MPP_BASE + 0x08); 92 writel(0x22222111, MVEBU_MPP_BASE + 0x0c); 93 writel(0x22200002, MVEBU_MPP_BASE + 0x10); 94 writel(0x30042022, MVEBU_MPP_BASE + 0x14); 95 writel(0x55550555, MVEBU_MPP_BASE + 0x18); 96 writel(0x00005550, MVEBU_MPP_BASE + 0x1c); 97 98 /* Set GPP Out value */ 99 writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); 100 writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); 101 102 /* Set GPP Polarity */ 103 writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); 104 writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); 105 106 /* Set GPP Out Enable */ 107 writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); 108 writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); 109 110 return 0; 111 } 112 113 int board_init(void) 114 { 115 int i; 116 117 /* adress of boot parameters */ 118 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 119 120 /* Init I2C IO expanders */ 121 for (i = 0; i < ARRAY_SIZE(io_exp); i++) 122 i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1); 123 124 return 0; 125 } 126 127 int checkboard(void) 128 { 129 puts("Board: Marvell DB-88F6820-GP\n"); 130 131 return 0; 132 } 133