1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015 Stefan Roese <sr@denx.de> 4 */ 5 6 #include <common.h> 7 #include <i2c.h> 8 #include <miiphy.h> 9 #include <netdev.h> 10 #include <asm/io.h> 11 #include <asm/arch/cpu.h> 12 #include <asm/arch/soc.h> 13 14 #include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h" 15 #include <../serdes/a38x/high_speed_env_spec.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 #define ETH_PHY_CTRL_REG 0 20 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11 21 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) 22 23 /* 24 * Those values and defines are taken from the Marvell U-Boot version 25 * "u-boot-2013.01-2016_T1.0.eng_drop_v10" 26 */ 27 #define DB_AMC_88F68XX_GPP_OUT_ENA_LOW \ 28 (~(BIT(29))) 29 #define DB_AMC_88F68XX_GPP_OUT_ENA_MID \ 30 (~(BIT(12) | BIT(17) | BIT(18) | BIT(20) | BIT(21))) 31 #define DB_AMC_88F68XX_GPP_OUT_VAL_LOW (BIT(29)) 32 #define DB_AMC_88F68XX_GPP_OUT_VAL_MID 0x0 33 #define DB_AMC_88F68XX_GPP_OUT_VAL_HIGH 0x0 34 #define DB_AMC_88F68XX_GPP_POL_LOW 0x0 35 #define DB_AMC_88F68XX_GPP_POL_MID 0x0 36 37 static struct serdes_map board_serdes_map[] = { 38 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 39 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 40 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 41 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 42 {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 43 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} 44 }; 45 46 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) 47 { 48 *serdes_map_array = board_serdes_map; 49 *count = ARRAY_SIZE(board_serdes_map); 50 return 0; 51 } 52 53 /* 54 * Define the DDR layout / topology here in the board file. This will 55 * be used by the DDR3 init code in the SPL U-Boot version to configure 56 * the DDR3 controller. 57 */ 58 static struct hws_topology_map board_topology_map = { 59 0x1, /* active interfaces */ 60 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ 61 { { { {0x1, 0, 0, 0}, 62 {0x1, 0, 0, 0}, 63 {0x1, 0, 0, 0}, 64 {0x1, 0, 0, 0}, 65 {0x1, 0, 0, 0} }, 66 SPEED_BIN_DDR_1866L, /* speed_bin */ 67 BUS_WIDTH_8, /* memory_width */ 68 MEM_2G, /* mem_size */ 69 DDR_FREQ_800, /* frequency */ 70 0, 0, /* cas_wl cas_l */ 71 HWS_TEMP_LOW, /* temperature */ 72 HWS_TIM_DEFAULT} }, /* timing */ 73 5, /* Num Of Bus Per Interface*/ 74 BUS_MASK_32BIT /* Busses mask */ 75 }; 76 77 struct hws_topology_map *ddr3_get_topology_map(void) 78 { 79 /* Return the board topology as defined in the board code */ 80 return &board_topology_map; 81 } 82 83 int board_early_init_f(void) 84 { 85 /* Configure MPP */ 86 writel(0x11111111, MVEBU_MPP_BASE + 0x00); 87 writel(0x11111111, MVEBU_MPP_BASE + 0x04); 88 writel(0x55066011, MVEBU_MPP_BASE + 0x08); 89 writel(0x05055550, MVEBU_MPP_BASE + 0x0c); 90 writel(0x05055555, MVEBU_MPP_BASE + 0x10); 91 writel(0x01106565, MVEBU_MPP_BASE + 0x14); 92 writel(0x40000000, MVEBU_MPP_BASE + 0x18); 93 writel(0x00004444, MVEBU_MPP_BASE + 0x1c); 94 95 /* Set GPP Out value */ 96 writel(DB_AMC_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); 97 writel(DB_AMC_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); 98 99 /* Set GPP Polarity */ 100 writel(DB_AMC_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); 101 writel(DB_AMC_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); 102 103 /* Set GPP Out Enable */ 104 writel(DB_AMC_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); 105 writel(DB_AMC_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); 106 107 return 0; 108 } 109 110 int board_init(void) 111 { 112 /* adress of boot parameters */ 113 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 114 115 return 0; 116 } 117 118 int checkboard(void) 119 { 120 puts("Board: Marvell DB-88F6820-AMC\n"); 121 122 return 0; 123 } 124 125 int board_eth_init(bd_t *bis) 126 { 127 cpu_eth_init(bis); /* Built in controller(s) come first */ 128 return pci_eth_init(bis); 129 } 130