1# 2# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> 3# 4# Based on Kirkwood support: 5# (C) Copyright 2009 6# Marvell Semiconductor <www.marvell.com> 7# Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8# 9# See file CREDITS for list of people who contributed to this 10# project. 11# 12# This program is free software; you can redistribute it and/or 13# modify it under the terms of the GNU General Public License as 14# published by the Free Software Foundation; either version 2 of 15# the License, or (at your option) any later version. 16# 17# This program is distributed in the hope that it will be useful, 18# but WITHOUT ANY WARRANTY; without even the implied warranty of 19# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20# GNU General Public License for more details. 21# 22# Refer doc/README.kwbimage for more details about how-to configure 23# and create kirkwood boot image 24# 25 26# Boot Media configurations 27BOOT_FROM spi # Boot from SPI flash 28 29# SOC registers configuration using bootrom header extension 30# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 31 32# Configure RGMII-0 interface pad voltage to 1.8V 33DATA 0xFFD100e0 0x1B1B1B9B 34 35#Dram initalization for SINGLE x16 CL=5 @ 400MHz 36DATA 0xFFD01400 0x43000618 # DDR Configuration register 37# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) 38# bit23-14: zero 39# bit24: 1= enable exit self refresh mode on DDR access 40# bit25: 1 required 41# bit29-26: zero 42# bit31-30: 01 43 44DATA 0xFFD01404 0x34143000 # DDR Controller Control Low 45# bit 4: 0=addr/cmd in smame cycle 46# bit 5: 0=clk is driven during self refresh, we don't care for APX 47# bit 6: 0=use recommended falling edge of clk for addr/cmd 48# bit14: 0=input buffer always powered up 49# bit18: 1=cpu lock transaction enabled 50# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 51# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 52# bit30-28: 3 required 53# bit31: 0=no additional STARTBURST delay 54 55DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) 56# bit7-4: TRCD 57# bit11- 8: TRP 58# bit15-12: TWR 59# bit19-16: TWTR 60# bit20: TRAS msb 61# bit23-21: 0x0 62# bit27-24: TRRD 63# bit31-28: TRTP 64 65DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) 66# bit6-0: TRFC 67# bit8-7: TR2R 68# bit10-9: TR2W 69# bit12-11: TW2W 70# bit31-13: zero required 71 72DATA 0xFFD01410 0x0000DDDD # DDR Address Control 73# bit1-0: 00, Cs0width=x8 74# bit3-2: 10, Cs0size=512Mb 75# bit5-4: 00, Cs2width=nonexistent 76# bit7-6: 00, Cs1size =nonexistent 77# bit9-8: 00, Cs2width=nonexistent 78# bit11-10: 00, Cs2size =nonexistent 79# bit13-12: 00, Cs3width=nonexistent 80# bit15-14: 00, Cs3size =nonexistent 81# bit16: 0, Cs0AddrSel 82# bit17: 0, Cs1AddrSel 83# bit18: 0, Cs2AddrSel 84# bit19: 0, Cs3AddrSel 85# bit31-20: 0 required 86 87DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 88# bit0: 0, OpenPage enabled 89# bit31-1: 0 required 90 91DATA 0xFFD01418 0x00000000 # DDR Operation 92# bit3-0: 0x0, DDR cmd 93# bit31-4: 0 required 94 95DATA 0xFFD0141C 0x00000632 # DDR Mode 96# bit2-0: 2, BurstLen=2 required 97# bit3: 0, BurstType=0 required 98# bit6-4: 4, CL=5 99# bit7: 0, TestMode=0 normal 100# bit8: 0, DLL reset=0 normal 101# bit11-9: 6, auto-precharge write recovery ???????????? 102# bit12: 0, PD must be zero 103# bit31-13: 0 required 104 105DATA 0xFFD01420 0x00000004 # DDR Extended Mode 106# bit0: 0, DDR DLL enabled 107# bit1: 1, DDR drive strenght reduced 108# bit2: 1, DDR ODT control lsd enabled 109# bit5-3: 000, required 110# bit6: 1, DDR ODT control msb, enabled 111# bit9-7: 000, required 112# bit10: 0, differential DQS enabled 113# bit11: 0, required 114# bit12: 0, DDR output buffer enabled 115# bit31-13: 0 required 116 117DATA 0xFFD01424 0x0000F07F # DDR Controller Control High 118# bit2-0: 111, required 119# bit3 : 1 , MBUS Burst Chop disabled 120# bit6-4: 111, required 121# bit7 : 1 , D2P Latency enabled 122# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz 123# bit9 : 0 , no half clock cycle addition to dataout 124# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 125# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 126# bit15-12: 1111 required 127# bit31-16: 0 required 128 129DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) 130DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) 131 132DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 133DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size 134# bit0: 1, Window enabled 135# bit1: 0, Write Protect disabled 136# bit3-2: 00, CS0 hit selected 137# bit23-4: ones, required 138# bit31-24: 0x07, Size (i.e. 128MB) 139 140DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 141DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 142DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 143 144DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) 145# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 146# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 147 148DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 149# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 150# bit3-2: 01, ODT1 active NEVER! 151# bit31-4: zero, required 152 153DATA 0xFFD0149C 0x0000E40F # CPU ODT Control 154# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 155# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 156# bit11-10:1, DQ_ODTSel. ODT select turned on 157 158DATA 0xFFD01480 0x00000001 # DDR Initialization Control 159#bit0=1, enable DDR init upon this register write 160 161# End of Header extension 162DATA 0x0 0x0 163