1*83d290c5STom Rini# SPDX-License-Identifier: GPL-2.0+ 2f697997aSSimon Guinot# 3f697997aSSimon Guinot# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> 4f697997aSSimon Guinot# 5f697997aSSimon Guinot# Based on Kirkwood support: 6f697997aSSimon Guinot# (C) Copyright 2009 7f697997aSSimon Guinot# Marvell Semiconductor <www.marvell.com> 8f697997aSSimon Guinot# Written-by: Prafulla Wadaskar <prafulla@marvell.com> 9b1e6c4c3SAnatolij Gustschin# Refer doc/README.kwbimage for more details about how-to configure 10f697997aSSimon Guinot# and create kirkwood boot image 11f697997aSSimon Guinot# 12f697997aSSimon Guinot 13f697997aSSimon Guinot# Boot Media configurations 14f697997aSSimon GuinotBOOT_FROM spi # Boot from SPI flash 15f697997aSSimon Guinot 16f697997aSSimon Guinot# SOC registers configuration using bootrom header extension 17f697997aSSimon Guinot# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 18f697997aSSimon Guinot 19f697997aSSimon Guinot# Configure RGMII-0 interface pad voltage to 1.8V 20f697997aSSimon GuinotDATA 0xFFD100e0 0x1B1B1B9B 21f697997aSSimon Guinot 22f697997aSSimon Guinot#Dram initalization for SINGLE x16 CL=5 @ 400MHz 23f697997aSSimon GuinotDATA 0xFFD01400 0x43000618 # DDR Configuration register 24f697997aSSimon Guinot# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) 25f697997aSSimon Guinot# bit23-14: zero 26f697997aSSimon Guinot# bit24: 1= enable exit self refresh mode on DDR access 27f697997aSSimon Guinot# bit25: 1 required 28f697997aSSimon Guinot# bit29-26: zero 29f697997aSSimon Guinot# bit31-30: 01 30f697997aSSimon Guinot 31f697997aSSimon GuinotDATA 0xFFD01404 0x35143000 # DDR Controller Control Low 32f697997aSSimon Guinot# bit 4: 0=addr/cmd in smame cycle 33f697997aSSimon Guinot# bit 5: 0=clk is driven during self refresh, we don't care for APX 34f697997aSSimon Guinot# bit 6: 0=use recommended falling edge of clk for addr/cmd 35f697997aSSimon Guinot# bit14: 0=input buffer always powered up 36f697997aSSimon Guinot# bit18: 1=cpu lock transaction enabled 37f697997aSSimon Guinot# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 38f697997aSSimon Guinot# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 39f697997aSSimon Guinot# bit30-28: 3 required 40f697997aSSimon Guinot# bit31: 0=no additional STARTBURST delay 41f697997aSSimon Guinot 42f697997aSSimon GuinotDATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) 43f697997aSSimon Guinot# bit7-4: TRCD 44f697997aSSimon Guinot# bit11- 8: TRP 45f697997aSSimon Guinot# bit15-12: TWR 46f697997aSSimon Guinot# bit19-16: TWTR 47f697997aSSimon Guinot# bit20: TRAS msb 48f697997aSSimon Guinot# bit23-21: 0x0 49f697997aSSimon Guinot# bit27-24: TRRD 50f697997aSSimon Guinot# bit31-28: TRTP 51f697997aSSimon Guinot 52f697997aSSimon GuinotDATA 0xFFD0140C 0x00000A19 # DDR Timing (High) 53f697997aSSimon Guinot# bit6-0: TRFC 54f697997aSSimon Guinot# bit8-7: TR2R 55f697997aSSimon Guinot# bit10-9: TR2W 56f697997aSSimon Guinot# bit12-11: TW2W 57f697997aSSimon Guinot# bit31-13: zero required 58f697997aSSimon Guinot 59f697997aSSimon GuinotDATA 0xFFD01410 0x00000008 # DDR Address Control 60f697997aSSimon Guinot# bit1-0: 00, Cs0width=x8 61f697997aSSimon Guinot# bit3-2: 10, Cs0size=512Mb 62f697997aSSimon Guinot# bit5-4: 00, Cs2width=nonexistent 63f697997aSSimon Guinot# bit7-6: 00, Cs1size =nonexistent 64f697997aSSimon Guinot# bit9-8: 00, Cs2width=nonexistent 65f697997aSSimon Guinot# bit11-10: 00, Cs2size =nonexistent 66f697997aSSimon Guinot# bit13-12: 00, Cs3width=nonexistent 67f697997aSSimon Guinot# bit15-14: 00, Cs3size =nonexistent 68f697997aSSimon Guinot# bit16: 0, Cs0AddrSel 69f697997aSSimon Guinot# bit17: 0, Cs1AddrSel 70f697997aSSimon Guinot# bit18: 0, Cs2AddrSel 71f697997aSSimon Guinot# bit19: 0, Cs3AddrSel 72f697997aSSimon Guinot# bit31-20: 0 required 73f697997aSSimon Guinot 74f697997aSSimon GuinotDATA 0xFFD01414 0x00000000 # DDR Open Pages Control 75f697997aSSimon Guinot# bit0: 0, OpenPage enabled 76f697997aSSimon Guinot# bit31-1: 0 required 77f697997aSSimon Guinot 78f697997aSSimon GuinotDATA 0xFFD01418 0x00000000 # DDR Operation 79f697997aSSimon Guinot# bit3-0: 0x0, DDR cmd 80f697997aSSimon Guinot# bit31-4: 0 required 81f697997aSSimon Guinot 82f697997aSSimon GuinotDATA 0xFFD0141C 0x00000632 # DDR Mode 83f697997aSSimon Guinot# bit2-0: 2, BurstLen=2 required 84f697997aSSimon Guinot# bit3: 0, BurstType=0 required 85f697997aSSimon Guinot# bit6-4: 4, CL=5 86f697997aSSimon Guinot# bit7: 0, TestMode=0 normal 87f697997aSSimon Guinot# bit8: 0, DLL reset=0 normal 88f697997aSSimon Guinot# bit11-9: 6, auto-precharge write recovery ???????????? 89f697997aSSimon Guinot# bit12: 0, PD must be zero 90f697997aSSimon Guinot# bit31-13: 0 required 91f697997aSSimon Guinot 92f697997aSSimon GuinotDATA 0xFFD01420 0x00000004 # DDR Extended Mode 93f697997aSSimon Guinot# bit0: 0, DDR DLL enabled 94f697997aSSimon Guinot# bit1: 1, DDR drive strenght reduced 95f697997aSSimon Guinot# bit2: 1, DDR ODT control lsd enabled 96f697997aSSimon Guinot# bit5-3: 000, required 97f697997aSSimon Guinot# bit6: 1, DDR ODT control msb, enabled 98f697997aSSimon Guinot# bit9-7: 000, required 99f697997aSSimon Guinot# bit10: 0, differential DQS enabled 100f697997aSSimon Guinot# bit11: 0, required 101f697997aSSimon Guinot# bit12: 0, DDR output buffer enabled 102f697997aSSimon Guinot# bit31-13: 0 required 103f697997aSSimon Guinot 104f697997aSSimon GuinotDATA 0xFFD01424 0x0000F07F # DDR Controller Control High 105f697997aSSimon Guinot# bit2-0: 111, required 106f697997aSSimon Guinot# bit3 : 1 , MBUS Burst Chop disabled 107f697997aSSimon Guinot# bit6-4: 111, required 108f697997aSSimon Guinot# bit7 : 1 , D2P Latency enabled 109f697997aSSimon Guinot# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz 110f697997aSSimon Guinot# bit9 : 0 , no half clock cycle addition to dataout 111f697997aSSimon Guinot# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 112f697997aSSimon Guinot# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 113f697997aSSimon Guinot# bit15-12: 1111 required 114f697997aSSimon Guinot# bit31-16: 0 required 115f697997aSSimon Guinot 116f697997aSSimon GuinotDATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) 117f697997aSSimon GuinotDATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) 118f697997aSSimon Guinot 119f697997aSSimon GuinotDATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 120f697997aSSimon GuinotDATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size 121f697997aSSimon Guinot# bit0: 1, Window enabled 122f697997aSSimon Guinot# bit1: 0, Write Protect disabled 123f697997aSSimon Guinot# bit3-2: 00, CS0 hit selected 124f697997aSSimon Guinot# bit23-4: ones, required 125f697997aSSimon Guinot# bit31-24: 0x07, Size (i.e. 128MB) 126f697997aSSimon Guinot 127f697997aSSimon GuinotDATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 128f697997aSSimon GuinotDATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 129f697997aSSimon GuinotDATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 130f697997aSSimon Guinot 131f697997aSSimon GuinotDATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) 132f697997aSSimon Guinot# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 133f697997aSSimon Guinot# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 134f697997aSSimon Guinot 135f697997aSSimon GuinotDATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 136f697997aSSimon Guinot# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 137f697997aSSimon Guinot# bit3-2: 01, ODT1 active NEVER! 138f697997aSSimon Guinot# bit31-4: zero, required 139f697997aSSimon Guinot 140f697997aSSimon GuinotDATA 0xFFD0149C 0x0000E40F # CPU ODT Control 141f697997aSSimon Guinot# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 142f697997aSSimon Guinot# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 143f697997aSSimon Guinot# bit11-10:1, DQ_ODTSel. ODT select turned on 144f697997aSSimon Guinot 145f697997aSSimon GuinotDATA 0xFFD01480 0x00000001 # DDR Initialization Control 146f697997aSSimon Guinot#bit0=1, enable DDR init upon this register write 147f697997aSSimon Guinot 148f697997aSSimon Guinot# End of Header extension 149f697997aSSimon GuinotDATA 0x0 0x0 150