1# 2# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> 3# 4# Based on Kirkwood support: 5# (C) Copyright 2009 6# Marvell Semiconductor <www.marvell.com> 7# Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8# 9# SPDX-License-Identifier: GPL-2.0+ 10# 11# Refer doc/README.kwbimage for more details about how-to configure 12# and create kirkwood boot image 13# 14 15# Boot Media configurations 16BOOT_FROM spi # Boot from SPI flash 17 18# SOC registers configuration using bootrom header extension 19# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 20 21# Configure RGMII-0 interface pad voltage to 1.8V 22DATA 0xFFD100e0 0x1B1B1B9B 23 24#Dram initalization for SINGLE x16 CL=5 @ 400MHz 25DATA 0xFFD01400 0x43000C30 # DDR Configuration register 26# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) 27# bit23-14: zero 28# bit24: 1= enable exit self refresh mode on DDR access 29# bit25: 1 required 30# bit29-26: zero 31# bit31-30: 01 32 33DATA 0xFFD01404 0x38743000 # DDR Controller Control Low 34# bit 4: 0=addr/cmd in smame cycle 35# bit 5: 0=clk is driven during self refresh, we don't care for APX 36# bit 6: 0=use recommended falling edge of clk for addr/cmd 37# bit14: 0=input buffer always powered up 38# bit18: 1=cpu lock transaction enabled 39# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 40# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 41# bit30-28: 3 required 42# bit31: 0=no additional STARTBURST delay 43 44DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) 45# bit7-4: TRCD 46# bit11- 8: TRP 47# bit15-12: TWR 48# bit19-16: TWTR 49# bit20: TRAS msb 50# bit23-21: 0x0 51# bit27-24: TRRD 52# bit31-28: TRTP 53 54DATA 0xFFD0140C 0x00000A32 # DDR Timing (High) 55# bit6-0: TRFC 56# bit8-7: TR2R 57# bit10-9: TR2W 58# bit12-11: TW2W 59# bit31-13: zero required 60 61DATA 0xFFD01410 0x0000CCCC # DDR Address Control 62# bit1-0: 01, Cs0width=x16 63# bit3-2: 11, Cs0size=1Gb 64# bit5-4: 00, Cs2width=nonexistent 65# bit7-6: 00, Cs1size =nonexistent 66# bit9-8: 00, Cs2width=nonexistent 67# bit11-10: 00, Cs2size =nonexistent 68# bit13-12: 00, Cs3width=nonexistent 69# bit15-14: 00, Cs3size =nonexistent 70# bit16: 0, Cs0AddrSel 71# bit17: 0, Cs1AddrSel 72# bit18: 0, Cs2AddrSel 73# bit19: 0, Cs3AddrSel 74# bit31-20: 0 required 75 76DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 77# bit0: 0, OpenPage enabled 78# bit31-1: 0 required 79 80DATA 0xFFD01418 0x00000000 # DDR Operation 81# bit3-0: 0x0, DDR cmd 82# bit31-4: 0 required 83 84DATA 0xFFD0141C 0x00000662 # DDR Mode 85# bit2-0: 2, BurstLen=2 required 86# bit3: 0, BurstType=0 required 87# bit6-4: 4, CL=5 88# bit7: 0, TestMode=0 normal 89# bit8: 0, DLL reset=0 normal 90# bit11-9: 6, auto-precharge write recovery ???????????? 91# bit12: 0, PD must be zero 92# bit31-13: 0 required 93 94DATA 0xFFD01420 0x00000044 # DDR Extended Mode 95# bit0: 0, DDR DLL enabled 96# bit1: 1, DDR drive strenght reduced 97# bit2: 1, DDR ODT control lsd enabled 98# bit5-3: 000, required 99# bit6: 1, DDR ODT control msb, enabled 100# bit9-7: 000, required 101# bit10: 0, differential DQS enabled 102# bit11: 0, required 103# bit12: 0, DDR output buffer enabled 104# bit31-13: 0 required 105 106DATA 0xFFD01424 0x0000F17F # DDR Controller Control High 107# bit2-0: 111, required 108# bit3 : 1 , MBUS Burst Chop disabled 109# bit6-4: 111, required 110# bit7 : 1 , D2P Latency enabled 111# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz 112# bit9 : 0 , no half clock cycle addition to dataout 113# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 114# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 115# bit15-12: 1111 required 116# bit31-16: 0 required 117 118DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) 119DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) 120 121DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 122DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size 123# bit0: 1, Window enabled 124# bit1: 0, Write Protect disabled 125# bit3-2: 00, CS0 hit selected 126# bit23-4: ones, required 127# bit31-24: 0x07, Size (i.e. 128MB) 128 129DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 130DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 131DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 132 133DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) 134# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 135# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 136 137DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 138# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 139# bit3-2: 01, ODT1 active NEVER! 140# bit31-4: zero, required 141 142DATA 0xFFD0149C 0x0000E40F # CPU ODT Control 143# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 144# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 145# bit11-10:1, DQ_ODTSel. ODT select turned on 146 147DATA 0xFFD01480 0x00000001 # DDR Initialization Control 148#bit0=1, enable DDR init upon this register write 149 150# End of Header extension 151DATA 0x0 0x0 152