1 /* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * (C) Copyright 2009 5 * Marvell Semiconductor <www.marvell.com> 6 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 24 * MA 02110-1301 USA 25 */ 26 27 #include <common.h> 28 #include <miiphy.h> 29 #include <asm/arch/orion5x.h> 30 #include "edminiv2.h" 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 /* 35 * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH 36 * which CFI does not properly detect, hence the LEGACY config. 37 */ 38 #if defined(CONFIG_FLASH_CFI_LEGACY) 39 #include <flash.h> 40 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) 41 { 42 int sectsz[] = CONFIG_SYS_FLASH_SECTSZ; 43 int sect; 44 45 if (base != CONFIG_SYS_FLASH_BASE) 46 return 0; 47 48 info->size = 0; 49 info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; 50 /* set each sector's start address and size based */ 51 for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) { 52 info->start[sect] = base+info->size; 53 info->size += sectsz[sect]; 54 } 55 /* This flash must be accessed in 8-bits mode, no buffer. */ 56 info->flash_id = 0x01000000; 57 info->portwidth = FLASH_CFI_8BIT; 58 info->chipwidth = FLASH_CFI_BY8; 59 info->buffer_size = 0; 60 /* timings are derived from the Macronix datasheet. */ 61 info->erase_blk_tout = 1000; 62 info->write_tout = 10; 63 info->buffer_write_tout = 300; 64 /* Commands and addresses are for AMD mode 8-bit access. */ 65 info->vendor = CFI_CMDSET_AMD_LEGACY; 66 info->cmd_reset = 0xF0; 67 info->interface = FLASH_CFI_X8; 68 info->legacy_unlock = 0; 69 info->ext_addr = 0; 70 info->addr_unlock1 = 0x00000aaa; 71 info->addr_unlock2 = 0x00000555; 72 /* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */ 73 info->manufacturer_id = 0x22; 74 info->device_id = 0xBA; 75 info->device_id2 = 0; 76 info->cfi_version = 0x3133; 77 info->cfi_offset = 0x0000; 78 info->name = "MX29LV400CB"; 79 80 return 1; 81 } 82 #endif /* CONFIG_SYS_FLASH_CFI */ 83 84 int board_init(void) 85 { 86 /* arch number of board */ 87 gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2; 88 89 /* boot parameter start at 256th byte of RAM base */ 90 gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; 91 92 return 0; 93 } 94 95 #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) 96 /* Configure and enable MV88E1116 PHY */ 97 void reset_phy(void) 98 { 99 u16 reg; 100 u16 devadr; 101 char *name = "egiga0"; 102 103 if (miiphy_set_current_dev(name)) 104 return; 105 106 /* command to read PHY dev address */ 107 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { 108 printf("Err..%s could not read PHY dev address\n", 109 __func__); 110 return; 111 } 112 113 /* 114 * Enable RGMII delay on Tx and Rx for CPU port 115 * Ref: sec 4.7.2 of chip datasheet 116 */ 117 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); 118 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); 119 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); 120 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); 121 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); 122 123 /* reset the phy */ 124 miiphy_reset(name, devadr); 125 126 printf("88E1116 Initialized on %s\n", name); 127 } 128 #endif /* CONFIG_RESET_PHY_R */ 129