1 /* 2 * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz> 3 * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz> 4 * 5 * Derived from the code for 6 * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <environment.h> 13 #include <i2c.h> 14 #include <miiphy.h> 15 #include <netdev.h> 16 #include <asm/io.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/soc.h> 19 #include <dm/uclass.h> 20 #include <fdt_support.h> 21 #include <time.h> 22 23 #ifdef CONFIG_ATSHA204A 24 # include <atsha204a-i2c.h> 25 #endif 26 27 #ifdef CONFIG_WDT_ORION 28 # include <wdt.h> 29 #endif 30 31 #include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h" 32 #include <../serdes/a38x/high_speed_env_spec.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #define OMNIA_I2C_EEPROM_DM_NAME "i2c@0" 37 #define OMNIA_I2C_EEPROM 0x54 38 #define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0 39 #define OMNIA_I2C_EEPROM_ADDRLEN 2 40 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034 41 42 #define OMNIA_I2C_MCU_DM_NAME "i2c@0" 43 #define OMNIA_I2C_MCU_ADDR_STATUS 0x1 44 #define OMNIA_I2C_MCU_SATA 0x20 45 #define OMNIA_I2C_MCU_CARDDET 0x10 46 #define OMNIA_I2C_MCU 0x2a 47 #define OMNIA_I2C_MCU_WDT_ADDR 0x0b 48 49 #define OMNIA_ATSHA204_OTP_VERSION 0 50 #define OMNIA_ATSHA204_OTP_SERIAL 1 51 #define OMNIA_ATSHA204_OTP_MAC0 3 52 #define OMNIA_ATSHA204_OTP_MAC1 4 53 54 #define MVTWSI_ARMADA_DEBUG_REG 0x8c 55 56 /* 57 * Those values and defines are taken from the Marvell U-Boot version 58 * "u-boot-2013.01-2014_T3.0" 59 */ 60 #define OMNIA_GPP_OUT_ENA_LOW \ 61 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \ 62 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \ 63 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31))) 64 #define OMNIA_GPP_OUT_ENA_MID \ 65 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \ 66 BIT(16) | BIT(17) | BIT(18))) 67 68 #define OMNIA_GPP_OUT_VAL_LOW 0x0 69 #define OMNIA_GPP_OUT_VAL_MID 0x0 70 #define OMNIA_GPP_POL_LOW 0x0 71 #define OMNIA_GPP_POL_MID 0x0 72 73 static struct serdes_map board_serdes_map_pex[] = { 74 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 75 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 76 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 77 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 78 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 79 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} 80 }; 81 82 static struct serdes_map board_serdes_map_sata[] = { 83 {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 84 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 85 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 86 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 87 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 88 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} 89 }; 90 91 static bool omnia_detect_sata(void) 92 { 93 struct udevice *bus, *dev; 94 int ret, retry = 3; 95 u16 mode; 96 97 puts("SERDES0 card detect: "); 98 99 if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { 100 puts("Cannot find MCU bus!\n"); 101 return false; 102 } 103 104 ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); 105 if (ret) { 106 puts("Cannot get MCU chip!\n"); 107 return false; 108 } 109 110 for (; retry > 0; --retry) { 111 ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2); 112 if (!ret) 113 break; 114 } 115 116 if (!retry) { 117 puts("I2C read failed! Default PEX\n"); 118 return false; 119 } 120 121 if (!(mode & OMNIA_I2C_MCU_CARDDET)) { 122 puts("NONE\n"); 123 return false; 124 } 125 126 if (mode & OMNIA_I2C_MCU_SATA) { 127 puts("SATA\n"); 128 return true; 129 } else { 130 puts("PEX\n"); 131 return false; 132 } 133 } 134 135 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) 136 { 137 if (omnia_detect_sata()) { 138 *serdes_map_array = board_serdes_map_sata; 139 *count = ARRAY_SIZE(board_serdes_map_sata); 140 } else { 141 *serdes_map_array = board_serdes_map_pex; 142 *count = ARRAY_SIZE(board_serdes_map_pex); 143 } 144 145 return 0; 146 } 147 148 struct omnia_eeprom { 149 u32 magic; 150 u32 ramsize; 151 char region[4]; 152 u32 crc; 153 }; 154 155 static bool omnia_read_eeprom(struct omnia_eeprom *oep) 156 { 157 struct udevice *bus, *dev; 158 int ret, crc, retry = 3; 159 160 if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_EEPROM_DM_NAME, &bus)) { 161 puts("Cannot find EEPROM bus\n"); 162 return false; 163 } 164 165 ret = i2c_get_chip(bus, OMNIA_I2C_EEPROM, OMNIA_I2C_EEPROM_ADDRLEN, &dev); 166 if (ret) { 167 puts("Cannot get EEPROM chip\n"); 168 return false; 169 } 170 171 for (; retry > 0; --retry) { 172 ret = dm_i2c_read(dev, OMNIA_I2C_EEPROM_CONFIG_ADDR, (uchar *) oep, sizeof(struct omnia_eeprom)); 173 if (ret) 174 continue; 175 176 if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) { 177 puts("I2C EEPROM missing magic number!\n"); 178 continue; 179 } 180 181 crc = crc32(0, (unsigned char *) oep, 182 sizeof(struct omnia_eeprom) - 4); 183 if (crc == oep->crc) { 184 break; 185 } else { 186 printf("CRC of EEPROM memory config failed! " 187 "calc=0x%04x saved=0x%04x\n", crc, oep->crc); 188 } 189 } 190 191 if (!retry) { 192 puts("I2C EEPROM read failed!\n"); 193 return false; 194 } 195 196 return true; 197 } 198 199 /* 200 * Define the DDR layout / topology here in the board file. This will 201 * be used by the DDR3 init code in the SPL U-Boot version to configure 202 * the DDR3 controller. 203 */ 204 static struct hws_topology_map board_topology_map_1g = { 205 0x1, /* active interfaces */ 206 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ 207 { { { {0x1, 0, 0, 0}, 208 {0x1, 0, 0, 0}, 209 {0x1, 0, 0, 0}, 210 {0x1, 0, 0, 0}, 211 {0x1, 0, 0, 0} }, 212 SPEED_BIN_DDR_1600K, /* speed_bin */ 213 BUS_WIDTH_16, /* memory_width */ 214 MEM_4G, /* mem_size */ 215 DDR_FREQ_800, /* frequency */ 216 0, 0, /* cas_wl cas_l */ 217 HWS_TEMP_NORMAL, /* temperature */ 218 HWS_TIM_2T} }, /* timing (force 2t) */ 219 5, /* Num Of Bus Per Interface*/ 220 BUS_MASK_32BIT /* Busses mask */ 221 }; 222 223 static struct hws_topology_map board_topology_map_2g = { 224 0x1, /* active interfaces */ 225 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ 226 { { { {0x1, 0, 0, 0}, 227 {0x1, 0, 0, 0}, 228 {0x1, 0, 0, 0}, 229 {0x1, 0, 0, 0}, 230 {0x1, 0, 0, 0} }, 231 SPEED_BIN_DDR_1600K, /* speed_bin */ 232 BUS_WIDTH_16, /* memory_width */ 233 MEM_8G, /* mem_size */ 234 DDR_FREQ_800, /* frequency */ 235 0, 0, /* cas_wl cas_l */ 236 HWS_TEMP_NORMAL, /* temperature */ 237 HWS_TIM_2T} }, /* timing (force 2t) */ 238 5, /* Num Of Bus Per Interface*/ 239 BUS_MASK_32BIT /* Busses mask */ 240 }; 241 242 struct hws_topology_map *ddr3_get_topology_map(void) 243 { 244 static int mem = 0; 245 struct omnia_eeprom oep; 246 247 /* Get the board config from EEPROM */ 248 if (mem == 0) { 249 if(!omnia_read_eeprom(&oep)) 250 goto out; 251 252 printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize); 253 254 if (oep.ramsize == 0x2) 255 mem = 2; 256 else 257 mem = 1; 258 } 259 260 out: 261 /* Hardcoded fallback */ 262 if (mem == 0) { 263 puts("WARNING: Memory config from EEPROM read failed.\n"); 264 puts("Falling back to default 1GiB map.\n"); 265 mem = 1; 266 } 267 268 /* Return the board topology as defined in the board code */ 269 if (mem == 1) 270 return &board_topology_map_1g; 271 if (mem == 2) 272 return &board_topology_map_2g; 273 274 return &board_topology_map_1g; 275 } 276 277 #ifndef CONFIG_SPL_BUILD 278 static int set_regdomain(void) 279 { 280 struct omnia_eeprom oep; 281 char rd[3] = {' ', ' ', 0}; 282 283 if (omnia_read_eeprom(&oep)) 284 memcpy(rd, &oep.region, 2); 285 else 286 puts("EEPROM regdomain read failed.\n"); 287 288 printf("Regdomain set to %s\n", rd); 289 return env_set("regdomain", rd); 290 } 291 #endif 292 293 int board_early_init_f(void) 294 { 295 u32 i2c_debug_reg; 296 297 /* Configure MPP */ 298 writel(0x11111111, MVEBU_MPP_BASE + 0x00); 299 writel(0x11111111, MVEBU_MPP_BASE + 0x04); 300 writel(0x11244011, MVEBU_MPP_BASE + 0x08); 301 writel(0x22222111, MVEBU_MPP_BASE + 0x0c); 302 writel(0x22200002, MVEBU_MPP_BASE + 0x10); 303 writel(0x30042022, MVEBU_MPP_BASE + 0x14); 304 writel(0x55550555, MVEBU_MPP_BASE + 0x18); 305 writel(0x00005550, MVEBU_MPP_BASE + 0x1c); 306 307 /* Set GPP Out value */ 308 writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); 309 writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); 310 311 /* Set GPP Polarity */ 312 writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); 313 writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); 314 315 /* Set GPP Out Enable */ 316 writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); 317 writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); 318 319 /* Disable I2C debug mode blocking 0x64 I2C address */ 320 i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); 321 i2c_debug_reg &= ~(1<<18); 322 writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); 323 324 return 0; 325 } 326 327 #ifndef CONFIG_SPL_BUILD 328 static bool disable_mcu_watchdog(void) 329 { 330 struct udevice *bus, *dev; 331 int ret, retry = 3; 332 uchar buf[1] = {0x0}; 333 334 if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { 335 puts("Cannot find MCU bus! Can not disable MCU WDT.\n"); 336 return false; 337 } 338 339 ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); 340 if (ret) { 341 puts("Cannot get MCU chip! Can not disable MCU WDT.\n"); 342 return false; 343 } 344 345 for (; retry > 0; --retry) 346 if (!dm_i2c_write(dev, OMNIA_I2C_MCU_WDT_ADDR, (uchar *) buf, 1)) 347 break; 348 349 if (retry <= 0) { 350 puts("I2C MCU watchdog failed to disable!\n"); 351 return false; 352 } 353 354 return true; 355 } 356 #endif 357 358 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) 359 static struct udevice *watchdog_dev = NULL; 360 #endif 361 362 int board_init(void) 363 { 364 /* adress of boot parameters */ 365 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 366 367 #ifndef CONFIG_SPL_BUILD 368 # ifdef CONFIG_WDT_ORION 369 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { 370 puts("Cannot find Armada 385 watchdog!\n"); 371 } else { 372 puts("Enabling Armada 385 watchdog.\n"); 373 wdt_start(watchdog_dev, (u32) 25000000 * 120, 0); 374 } 375 # endif 376 377 if (disable_mcu_watchdog()) 378 puts("Disabled MCU startup watchdog.\n"); 379 380 set_regdomain(); 381 #endif 382 383 return 0; 384 } 385 386 #ifdef CONFIG_WATCHDOG 387 /* Called by macro WATCHDOG_RESET */ 388 void watchdog_reset(void) 389 { 390 # if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) 391 static ulong next_reset = 0; 392 ulong now; 393 394 if (!watchdog_dev) 395 return; 396 397 now = timer_get_us(); 398 399 /* Do not reset the watchdog too often */ 400 if (now > next_reset) { 401 wdt_reset(watchdog_dev); 402 next_reset = now + 1000; 403 } 404 # endif 405 } 406 #endif 407 408 int board_late_init(void) 409 { 410 #ifndef CONFIG_SPL_BUILD 411 set_regdomain(); 412 #endif 413 414 return 0; 415 } 416 417 #ifdef CONFIG_ATSHA204A 418 static struct udevice *get_atsha204a_dev(void) 419 { 420 static struct udevice *dev = NULL; 421 422 if (dev != NULL) 423 return dev; 424 425 if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { 426 puts("Cannot find ATSHA204A on I2C bus!\n"); 427 dev = NULL; 428 } 429 430 return dev; 431 } 432 #endif 433 434 int checkboard(void) 435 { 436 u32 version_num, serial_num; 437 int err = 1; 438 439 #ifdef CONFIG_ATSHA204A 440 struct udevice *dev = get_atsha204a_dev(); 441 442 if (dev) { 443 err = atsha204a_wakeup(dev); 444 if (err) 445 goto out; 446 447 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, 448 OMNIA_ATSHA204_OTP_VERSION, 449 (u8 *) &version_num); 450 if (err) 451 goto out; 452 453 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, 454 OMNIA_ATSHA204_OTP_SERIAL, 455 (u8 *) &serial_num); 456 if (err) 457 goto out; 458 459 atsha204a_sleep(dev); 460 } 461 462 out: 463 #endif 464 465 if (err) 466 printf("Board: Turris Omnia (ver N/A). SN: N/A\n"); 467 else 468 printf("Board: Turris Omnia SNL %08X%08X\n", 469 be32_to_cpu(version_num), be32_to_cpu(serial_num)); 470 471 return 0; 472 } 473 474 static void increment_mac(u8 *mac) 475 { 476 int i; 477 478 for (i = 5; i >= 3; i--) { 479 mac[i] += 1; 480 if (mac[i]) 481 break; 482 } 483 } 484 485 int misc_init_r(void) 486 { 487 #ifdef CONFIG_ATSHA204A 488 int err; 489 struct udevice *dev = get_atsha204a_dev(); 490 u8 mac0[4], mac1[4], mac[6]; 491 492 if (!dev) 493 goto out; 494 495 err = atsha204a_wakeup(dev); 496 if (err) 497 goto out; 498 499 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, 500 OMNIA_ATSHA204_OTP_MAC0, mac0); 501 if (err) 502 goto out; 503 504 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, 505 OMNIA_ATSHA204_OTP_MAC1, mac1); 506 if (err) 507 goto out; 508 509 atsha204a_sleep(dev); 510 511 mac[0] = mac0[1]; 512 mac[1] = mac0[2]; 513 mac[2] = mac0[3]; 514 mac[3] = mac1[1]; 515 mac[4] = mac1[2]; 516 mac[5] = mac1[3]; 517 518 if (is_valid_ethaddr(mac)) 519 eth_env_set_enetaddr("ethaddr", mac); 520 521 increment_mac(mac); 522 523 if (is_valid_ethaddr(mac)) 524 eth_env_set_enetaddr("eth1addr", mac); 525 526 increment_mac(mac); 527 528 if (is_valid_ethaddr(mac)) 529 eth_env_set_enetaddr("eth2addr", mac); 530 531 out: 532 #endif 533 534 return 0; 535 } 536 537