1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * mux.c
4 *
5 * Pinmux Setting for B&R LEIT Board(s)
6 *
7 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
8 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
9 */
10
11 #include <common.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/mux.h>
15 #include <asm/io.h>
16 #include <i2c.h>
17
18 static struct module_pin_mux spi0_pin_mux[] = {
19 /* SPI1_SCLK */
20 {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
21 /* SPI1_D0 */
22 {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
23 /* SPI1_D1 */
24 {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
25 /* SPI1_CS0 */
26 {OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
27 /* SPI1_CS1 */
28 {OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
29 {-1},
30 };
31
32 static struct module_pin_mux dcan0_pin_mux[] = {
33 /* DCAN0 TX */
34 {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
35 /* DCAN0 RX */
36 {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
37 {-1},
38 };
39
40 static struct module_pin_mux dcan1_pin_mux[] = {
41 /* DCAN1 TX */
42 {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN},
43 /* DCAN1 RX */
44 {OFFSET(uart1_txd), MODE(2) | RXACTIVE},
45 {-1},
46 };
47
48 static struct module_pin_mux gpios[] = {
49 /* GPIO0_7 (PWW0 OUT) - CAN TERM */
50 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
51 /* GPIO0_19 (DMA_INTR0) - TA602 */
52 {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
53 /* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */
54 {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
55 /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
56 {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
57 /* GPIO0_30 (GPMC_WAIT0) - TA601 */
58 {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
59 /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
60 {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
61 /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
62 {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
63 /* GPIO1_29 (gpmc_csn0) - MMC nRST */
64 {OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)},
65 /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */
66 {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
67 /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */
68 {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
69 /* GPIO2_4 (GPMC_nWE) - TST_BAST */
70 {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
71 /* GPIO2_5 (gpmc_be0n_cle) - DISPLAY_ON_OFF */
72 {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},
73 /* GPIO3_16 (mcasp0_axr0) - ETH-LED green */
74 {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
75 /* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */
76 {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
77 /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
78 {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
79 /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
80 {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
81 /* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
82 {OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
83 {-1},
84 };
85
86 static struct module_pin_mux uart0_pin_mux[] = {
87 /* UART0_CTS */
88 {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
89 /* UART0_RXD */
90 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
91 /* UART0_TXD */
92 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
93 {-1},
94 };
95
96 static struct module_pin_mux i2c0_pin_mux[] = {
97 /* I2C_DATA */
98 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
99 /* I2C_SCLK */
100 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
101 {-1},
102 };
103
104 static struct module_pin_mux mii1_pin_mux[] = {
105 {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
106 {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
107 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
108 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
109 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
110 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
111 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
112 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
113 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
114 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
115 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
116 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
117 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
118 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
119 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
120 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
121 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
122 {-1},
123 };
124
125 static struct module_pin_mux mmc1_pin_mux[] = {
126 {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
127 {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
128 {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
129 {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
130 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
131 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
132 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
133 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
134 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
135 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
136 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
137 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
138
139 {-1},
140 };
141
142 static struct module_pin_mux lcd_pin_mux[] = {
143 {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
144 {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
145 {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
146 {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
147 {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
148 {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
149 {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
150 {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
151 {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
152 {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
153 {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
154 {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
155 {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
156 {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
157 {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
158 {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
159
160 {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
161 {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
162 {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
163 {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
164 {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
165 {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
166 {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
167 {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
168
169 {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
170 {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
171 {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
172 {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
173
174 {-1},
175 };
176
enable_uart0_pin_mux(void)177 void enable_uart0_pin_mux(void)
178 {
179 configure_module_pin_mux(uart0_pin_mux);
180 }
181
enable_i2c_pin_mux(void)182 void enable_i2c_pin_mux(void)
183 {
184 configure_module_pin_mux(i2c0_pin_mux);
185 }
186
enable_board_pin_mux(void)187 void enable_board_pin_mux(void)
188 {
189 configure_module_pin_mux(i2c0_pin_mux);
190 configure_module_pin_mux(mii1_pin_mux);
191 configure_module_pin_mux(spi0_pin_mux);
192 configure_module_pin_mux(dcan0_pin_mux);
193 configure_module_pin_mux(dcan1_pin_mux);
194 configure_module_pin_mux(mmc1_pin_mux);
195 configure_module_pin_mux(lcd_pin_mux);
196 configure_module_pin_mux(gpios);
197 }
198