1 /* 2 * board.c 3 * 4 * Board functions for B&R BRXRE1 Board 5 * 6 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> 7 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 * 11 */ 12 #include <common.h> 13 #include <errno.h> 14 #include <spl.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/arch/omap.h> 18 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/gpio.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/mem.h> 23 #include <asm/io.h> 24 #include <asm/emif.h> 25 #include <asm/gpio.h> 26 #include <i2c.h> 27 #include <power/tps65217.h> 28 #include "../common/bur_common.h" 29 #include <lcd.h> 30 31 /* -------------------------------------------------------------------------*/ 32 /* -- defines for used GPIO Hardware -- */ 33 #define ESC_KEY (0+19) 34 #define LCD_PWR (0+5) 35 #define PUSH_KEY (0+31) 36 /* -------------------------------------------------------------------------*/ 37 /* -- PSOC Resetcontroller Register defines -- */ 38 39 /* I2C Address of controller */ 40 #define RSTCTRL_ADDR 0x75 41 /* Register for CTRL-word */ 42 #define RSTCTRL_CTRLREG 0x01 43 /* Register for giving some information to VxWorks OS */ 44 #define RSTCTRL_SCRATCHREG 0x04 45 46 /* -- defines for RSTCTRL_CTRLREG -- */ 47 #define RSTCTRL_FORCE_PWR_NEN 0x0404 48 #define RSTCTRL_CAN_STB 0x4040 49 50 DECLARE_GLOBAL_DATA_PTR; 51 52 #if defined(CONFIG_SPL_BUILD) 53 /* TODO: check ram-timing ! */ 54 static const struct ddr_data ddr3_data = { 55 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 56 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 57 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 58 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 59 }; 60 static const struct cmd_control ddr3_cmd_ctrl_data = { 61 .cmd0csratio = MT41K256M16HA125E_RATIO, 62 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 63 64 .cmd1csratio = MT41K256M16HA125E_RATIO, 65 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 66 67 .cmd2csratio = MT41K256M16HA125E_RATIO, 68 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 69 }; 70 static struct emif_regs ddr3_emif_reg_data = { 71 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 72 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 73 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 74 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 75 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 76 .zq_config = MT41K256M16HA125E_ZQ_CFG, 77 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 78 }; 79 80 static const struct ctrl_ioregs ddr3_ioregs = { 81 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 82 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 83 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 84 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 85 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 86 }; 87 88 #define OSC (V_OSCK/1000000) 89 const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; 90 91 void am33xx_spl_board_init(void) 92 { 93 unsigned int oldspeed; 94 unsigned short buf; 95 96 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; 97 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; 98 /* 99 * enable additional clocks of modules which are accessed later from 100 * VxWorks OS 101 */ 102 u32 *const clk_domains[] = { 0 }; 103 104 u32 *const clk_modules_xre1specific[] = { 105 &cmwkup->wkup_adctscctrl, 106 &cmper->spi1clkctrl, 107 &cmper->dcan0clkctrl, 108 &cmper->dcan1clkctrl, 109 &cmper->epwmss0clkctrl, 110 &cmper->epwmss1clkctrl, 111 &cmper->epwmss2clkctrl, 112 &cmper->lcdclkctrl, 113 &cmper->lcdcclkstctrl, 114 0 115 }; 116 do_enable_clocks(clk_domains, clk_modules_xre1specific, 1); 117 /* power-OFF LCD-Display */ 118 gpio_direction_output(LCD_PWR, 0); 119 120 /* setup I2C */ 121 enable_i2c_pin_mux(); 122 i2c_set_bus_num(0); 123 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 124 125 /* power-ON 3V3 via Resetcontroller */ 126 oldspeed = i2c_get_bus_speed(); 127 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { 128 buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB; 129 i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1, 130 (uint8_t *)&buf, sizeof(buf)); 131 i2c_set_bus_speed(oldspeed); 132 } else { 133 puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n"); 134 } 135 136 pmicsetup(0); 137 } 138 139 const struct dpll_params *get_dpll_ddr_params(void) 140 { 141 return &dpll_ddr3; 142 } 143 144 void sdram_init(void) 145 { 146 config_ddr(400, &ddr3_ioregs, 147 &ddr3_data, 148 &ddr3_cmd_ctrl_data, 149 &ddr3_emif_reg_data, 0); 150 } 151 #endif /* CONFIG_SPL_BUILD */ 152 /* 153 * Basic board specific setup. Pinmux has been handled already. 154 */ 155 int board_init(void) 156 { 157 gpmc_init(); 158 return 0; 159 } 160 161 #ifdef CONFIG_BOARD_LATE_INIT 162 int board_late_init(void) 163 { 164 const unsigned int toff = 1000; 165 unsigned int cnt = 3; 166 unsigned short buf = 0xAAAA; 167 unsigned char scratchreg = 0; 168 unsigned int oldspeed; 169 170 /* try to read out some boot-instruction from resetcontroller */ 171 oldspeed = i2c_get_bus_speed(); 172 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { 173 i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, 174 &scratchreg, sizeof(scratchreg)); 175 i2c_set_bus_speed(oldspeed); 176 } else { 177 puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); 178 } 179 180 if (gpio_get_value(ESC_KEY)) { 181 do { 182 lcd_position_cursor(1, 8); 183 switch (cnt) { 184 case 3: 185 lcd_puts( 186 "release ESC-KEY to enter SERVICE-mode."); 187 break; 188 case 2: 189 lcd_puts( 190 "release ESC-KEY to enter DIAGNOSE-mode."); 191 break; 192 case 1: 193 lcd_puts( 194 "release ESC-KEY to enter BOOT-mode. "); 195 break; 196 } 197 mdelay(toff); 198 cnt--; 199 if (!gpio_get_value(ESC_KEY) && 200 gpio_get_value(PUSH_KEY) && 2 == cnt) { 201 lcd_position_cursor(1, 8); 202 lcd_puts( 203 "switching to network-console ... "); 204 env_set("bootcmd", "run netconsole"); 205 cnt = 4; 206 break; 207 } else if (!gpio_get_value(ESC_KEY) && 208 gpio_get_value(PUSH_KEY) && 1 == cnt) { 209 lcd_position_cursor(1, 8); 210 lcd_puts( 211 "starting u-boot script from USB ... "); 212 env_set("bootcmd", "run usbscript"); 213 cnt = 4; 214 break; 215 } else if ((!gpio_get_value(ESC_KEY) && 216 gpio_get_value(PUSH_KEY) && cnt == 0) || 217 (gpio_get_value(ESC_KEY) && 218 gpio_get_value(PUSH_KEY) && cnt == 0)) { 219 lcd_position_cursor(1, 8); 220 lcd_puts( 221 "starting script from network ... "); 222 env_set("bootcmd", "run netscript"); 223 cnt = 4; 224 break; 225 } else if (!gpio_get_value(ESC_KEY)) { 226 break; 227 } 228 } while (cnt); 229 } else if (scratchreg == 0xCC) { 230 lcd_position_cursor(1, 8); 231 lcd_puts( 232 "starting vxworks from network ... "); 233 env_set("bootcmd", "run netboot"); 234 cnt = 4; 235 } else if (scratchreg == 0xCD) { 236 lcd_position_cursor(1, 8); 237 lcd_puts( 238 "starting script from network ... "); 239 env_set("bootcmd", "run netscript"); 240 cnt = 4; 241 } else if (scratchreg == 0xCE) { 242 lcd_position_cursor(1, 8); 243 lcd_puts( 244 "starting AR from eMMC ... "); 245 env_set("bootcmd", "run mmcboot"); 246 cnt = 4; 247 } 248 249 lcd_position_cursor(1, 8); 250 switch (cnt) { 251 case 0: 252 lcd_puts("entering BOOT-mode. "); 253 env_set("bootcmd", "run defaultAR"); 254 buf = 0x0000; 255 break; 256 case 1: 257 lcd_puts("entering DIAGNOSE-mode. "); 258 buf = 0x0F0F; 259 break; 260 case 2: 261 lcd_puts("entering SERVICE mode. "); 262 buf = 0xB4B4; 263 break; 264 case 3: 265 lcd_puts("loading OS... "); 266 buf = 0x0404; 267 break; 268 } 269 /* write bootinfo into scratchregister of resetcontroller */ 270 oldspeed = i2c_get_bus_speed(); 271 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { 272 i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, 273 (uint8_t *)&buf, sizeof(buf)); 274 i2c_set_bus_speed(oldspeed); 275 } else { 276 puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); 277 } 278 /* setup othbootargs for bootvx-command (vxWorks bootline) */ 279 char othbootargs[128]; 280 snprintf(othbootargs, sizeof(othbootargs), 281 "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x", 282 (unsigned int) gd->fb_base-0x20, 283 (u32)env_get_ulong("vx_memtop", 16, gd->fb_base-0x20), 284 (u32)env_get_ulong("vx_romfsbase", 16, 0), 285 (u32)env_get_ulong("vx_romfssize", 16, 0)); 286 env_set("othbootargs", othbootargs); 287 /* 288 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does 289 * expect that vectors are there, original u-boot moves them to _start 290 */ 291 __asm__("ldr r0,=0x20000"); 292 __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */ 293 294 return 0; 295 } 296 #endif /* CONFIG_BOARD_LATE_INIT */ 297