1 /* 2 * board.c 3 * 4 * Board functions for B&R BRXRE1 Board 5 * 6 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> 7 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 * 11 */ 12 #include <common.h> 13 #include <errno.h> 14 #include <spl.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/arch/omap.h> 18 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/gpio.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/mem.h> 23 #include <asm/io.h> 24 #include <asm/emif.h> 25 #include <asm/gpio.h> 26 #include <i2c.h> 27 #include <power/tps65217.h> 28 #include "../common/bur_common.h" 29 #include <lcd.h> 30 31 /* -------------------------------------------------------------------------*/ 32 /* -- defines for used GPIO Hardware -- */ 33 #define ESC_KEY (0+19) 34 #define LCD_PWR (0+5) 35 #define PUSH_KEY (0+31) 36 /* -------------------------------------------------------------------------*/ 37 /* -- PSOC Resetcontroller Register defines -- */ 38 39 /* I2C Address of controller */ 40 #define RSTCTRL_ADDR 0x75 41 /* Register for CTRL-word */ 42 #define RSTCTRL_CTRLREG 0x01 43 /* Register for giving some information to VxWorks OS */ 44 #define RSTCTRL_SCRATCHREG 0x04 45 46 /* -- defines for RSTCTRL_CTRLREG -- */ 47 #define RSTCTRL_FORCE_PWR_NEN 0x0404 48 #define RSTCTRL_CAN_STB 0x4040 49 50 DECLARE_GLOBAL_DATA_PTR; 51 52 #if defined(CONFIG_SPL_BUILD) 53 /* TODO: check ram-timing ! */ 54 static const struct ddr_data ddr3_data = { 55 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 56 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 57 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 58 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 59 }; 60 static const struct cmd_control ddr3_cmd_ctrl_data = { 61 .cmd0csratio = MT41K256M16HA125E_RATIO, 62 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 63 64 .cmd1csratio = MT41K256M16HA125E_RATIO, 65 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 66 67 .cmd2csratio = MT41K256M16HA125E_RATIO, 68 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 69 }; 70 static struct emif_regs ddr3_emif_reg_data = { 71 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 72 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 73 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 74 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 75 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 76 .zq_config = MT41K256M16HA125E_ZQ_CFG, 77 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 78 }; 79 80 static const struct ctrl_ioregs ddr3_ioregs = { 81 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 82 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 83 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 84 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 85 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 86 }; 87 88 #define OSC (V_OSCK/1000000) 89 const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; 90 91 void am33xx_spl_board_init(void) 92 { 93 unsigned int oldspeed; 94 unsigned short buf; 95 96 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; 97 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; 98 /* 99 * enable additional clocks of modules which are accessed later from 100 * VxWorks OS 101 */ 102 u32 *const clk_domains[] = { 0 }; 103 104 u32 *const clk_modules_xre1specific[] = { 105 &cmwkup->wkup_adctscctrl, 106 &cmper->spi1clkctrl, 107 &cmper->dcan0clkctrl, 108 &cmper->dcan1clkctrl, 109 &cmper->epwmss0clkctrl, 110 &cmper->epwmss1clkctrl, 111 &cmper->epwmss2clkctrl, 112 &cmper->lcdclkctrl, 113 &cmper->lcdcclkstctrl, 114 0 115 }; 116 do_enable_clocks(clk_domains, clk_modules_xre1specific, 1); 117 /* setup LCD-Pixel Clock */ 118 writel(0x2, CM_DPLL + 0x34); 119 /* power-OFF LCD-Display */ 120 gpio_direction_output(LCD_PWR, 0); 121 122 /* setup I2C */ 123 enable_i2c_pin_mux(); 124 i2c_set_bus_num(0); 125 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 126 127 /* power-ON 3V3 via Resetcontroller */ 128 oldspeed = i2c_get_bus_speed(); 129 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { 130 buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB; 131 i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1, 132 (uint8_t *)&buf, sizeof(buf)); 133 i2c_set_bus_speed(oldspeed); 134 } else { 135 puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n"); 136 } 137 138 pmicsetup(0); 139 } 140 141 const struct dpll_params *get_dpll_ddr_params(void) 142 { 143 return &dpll_ddr3; 144 } 145 146 void sdram_init(void) 147 { 148 config_ddr(400, &ddr3_ioregs, 149 &ddr3_data, 150 &ddr3_cmd_ctrl_data, 151 &ddr3_emif_reg_data, 0); 152 } 153 #endif /* CONFIG_SPL_BUILD */ 154 /* 155 * Basic board specific setup. Pinmux has been handled already. 156 */ 157 int board_init(void) 158 { 159 gpmc_init(); 160 return 0; 161 } 162 163 #ifdef CONFIG_BOARD_LATE_INIT 164 int board_late_init(void) 165 { 166 const unsigned int toff = 1000; 167 unsigned int cnt = 3; 168 unsigned short buf = 0xAAAA; 169 unsigned char scratchreg = 0; 170 unsigned int oldspeed; 171 172 /* try to read out some boot-instruction from resetcontroller */ 173 oldspeed = i2c_get_bus_speed(); 174 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { 175 i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, 176 &scratchreg, sizeof(scratchreg)); 177 i2c_set_bus_speed(oldspeed); 178 } else { 179 puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); 180 } 181 182 if (gpio_get_value(ESC_KEY)) { 183 do { 184 lcd_position_cursor(1, 8); 185 switch (cnt) { 186 case 3: 187 lcd_puts( 188 "release ESC-KEY to enter SERVICE-mode."); 189 break; 190 case 2: 191 lcd_puts( 192 "release ESC-KEY to enter DIAGNOSE-mode."); 193 break; 194 case 1: 195 lcd_puts( 196 "release ESC-KEY to enter BOOT-mode. "); 197 break; 198 } 199 mdelay(toff); 200 cnt--; 201 if (!gpio_get_value(ESC_KEY) && 202 gpio_get_value(PUSH_KEY) && 2 == cnt) { 203 lcd_position_cursor(1, 8); 204 lcd_puts( 205 "switching to network-console ... "); 206 env_set("bootcmd", "run netconsole"); 207 cnt = 4; 208 break; 209 } else if (!gpio_get_value(ESC_KEY) && 210 gpio_get_value(PUSH_KEY) && 1 == cnt) { 211 lcd_position_cursor(1, 8); 212 lcd_puts( 213 "starting u-boot script from USB ... "); 214 env_set("bootcmd", "run usbscript"); 215 cnt = 4; 216 break; 217 } else if ((!gpio_get_value(ESC_KEY) && 218 gpio_get_value(PUSH_KEY) && cnt == 0) || 219 (gpio_get_value(ESC_KEY) && 220 gpio_get_value(PUSH_KEY) && cnt == 0)) { 221 lcd_position_cursor(1, 8); 222 lcd_puts( 223 "starting script from network ... "); 224 env_set("bootcmd", "run netscript"); 225 cnt = 4; 226 break; 227 } else if (!gpio_get_value(ESC_KEY)) { 228 break; 229 } 230 } while (cnt); 231 } else if (scratchreg == 0xCC) { 232 lcd_position_cursor(1, 8); 233 lcd_puts( 234 "starting vxworks from network ... "); 235 env_set("bootcmd", "run netboot"); 236 cnt = 4; 237 } else if (scratchreg == 0xCD) { 238 lcd_position_cursor(1, 8); 239 lcd_puts( 240 "starting script from network ... "); 241 env_set("bootcmd", "run netscript"); 242 cnt = 4; 243 } else if (scratchreg == 0xCE) { 244 lcd_position_cursor(1, 8); 245 lcd_puts( 246 "starting AR from eMMC ... "); 247 env_set("bootcmd", "run mmcboot"); 248 cnt = 4; 249 } 250 251 lcd_position_cursor(1, 8); 252 switch (cnt) { 253 case 0: 254 lcd_puts("entering BOOT-mode. "); 255 env_set("bootcmd", "run defaultAR"); 256 buf = 0x0000; 257 break; 258 case 1: 259 lcd_puts("entering DIAGNOSE-mode. "); 260 buf = 0x0F0F; 261 break; 262 case 2: 263 lcd_puts("entering SERVICE mode. "); 264 buf = 0xB4B4; 265 break; 266 case 3: 267 lcd_puts("loading OS... "); 268 buf = 0x0404; 269 break; 270 } 271 /* write bootinfo into scratchregister of resetcontroller */ 272 oldspeed = i2c_get_bus_speed(); 273 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { 274 i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, 275 (uint8_t *)&buf, sizeof(buf)); 276 i2c_set_bus_speed(oldspeed); 277 } else { 278 puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); 279 } 280 /* setup othbootargs for bootvx-command (vxWorks bootline) */ 281 char othbootargs[128]; 282 snprintf(othbootargs, sizeof(othbootargs), 283 "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x", 284 (unsigned int) gd->fb_base-0x20, 285 (u32)env_get_ulong("vx_memtop", 16, gd->fb_base-0x20), 286 (u32)env_get_ulong("vx_romfsbase", 16, 0), 287 (u32)env_get_ulong("vx_romfssize", 16, 0)); 288 env_set("othbootargs", othbootargs); 289 /* 290 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does 291 * expect that vectors are there, original u-boot moves them to _start 292 */ 293 __asm__("ldr r0,=0x20000"); 294 __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */ 295 296 return 0; 297 } 298 #endif /* CONFIG_BOARD_LATE_INIT */ 299