1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * mux.c 4 * 5 * Pinmux Setting for B&R BRPPT1 Board(s) 6 * 7 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> 8 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com 9 */ 10 11 #include <common.h> 12 #include <asm/arch/sys_proto.h> 13 #include <asm/arch/hardware.h> 14 #include <asm/arch/mux.h> 15 #include <asm/io.h> 16 #include <i2c.h> 17 18 static struct module_pin_mux uart0_pin_mux[] = { 19 /* UART0_RTS */ 20 {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)}, 21 /* UART0_CTS */ 22 {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, 23 /* UART0_RXD */ 24 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, 25 /* UART0_TXD */ 26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, 27 {-1}, 28 }; 29 static struct module_pin_mux uart1_pin_mux[] = { 30 /* UART1_RTS as I2C2-SCL */ 31 {OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)}, 32 /* UART1_CTS as I2C2-SDA */ 33 {OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)}, 34 /* UART1_RXD */ 35 {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, 36 /* UART1_TXD */ 37 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, 38 {-1}, 39 }; 40 #ifdef CONFIG_MMC 41 static struct module_pin_mux mmc1_pin_mux[] = { 42 {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ 43 {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ 44 {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ 45 {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ 46 47 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ 48 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ 49 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ 50 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ 51 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ 52 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ 53 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ 54 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ 55 {-1}, 56 }; 57 #endif 58 static struct module_pin_mux i2c0_pin_mux[] = { 59 /* I2C_DATA */ 60 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, 61 /* I2C_SCLK */ 62 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, 63 {-1}, 64 }; 65 66 static struct module_pin_mux spi0_pin_mux[] = { 67 /* SPI0_SCLK */ 68 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, 69 /* SPI0_D0 */ 70 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, 71 /* SPI0_D1 */ 72 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, 73 /* SPI0_CS0 */ 74 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, 75 {-1}, 76 }; 77 78 static struct module_pin_mux mii1_pin_mux[] = { 79 {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ 80 {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ 81 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ 82 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ 83 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ 84 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ 85 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ 86 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ 87 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ 88 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ 89 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ 90 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ 91 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ 92 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ 93 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ 94 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ 95 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 96 {-1}, 97 }; 98 99 static struct module_pin_mux mii2_pin_mux[] = { 100 {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */ 101 {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */ 102 {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */ 103 {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */ 104 {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */ 105 {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */ 106 {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */ 107 {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */ 108 {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */ 109 {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */ 110 {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */ 111 {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */ 112 {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */ 113 {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)}, 114 /* 115 * MII2_CRS is shared with 116 * NAND_WAIT0 117 */ 118 {OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */ 119 {-1}, 120 }; 121 #ifdef CONFIG_NAND 122 static struct module_pin_mux nand_pin_mux[] = { 123 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ 124 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ 125 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ 126 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ 127 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ 128 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ 129 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ 130 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ 131 {OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ 132 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ 133 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ 134 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ 135 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ 136 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ 137 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ 138 {-1}, 139 }; 140 #endif 141 static struct module_pin_mux gpIOs[] = { 142 /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */ 143 {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, 144 /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */ 145 {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)}, 146 /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */ 147 {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)}, 148 /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */ 149 {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)}, 150 /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */ 151 {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)}, 152 /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */ 153 {OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, 154 /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */ 155 {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, 156 /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */ 157 {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, 158 /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */ 159 {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, 160 /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */ 161 {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, 162 /* GPIO2_0 (GPMC_nCS3) - DCOK */ 163 {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, 164 /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ 165 {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) }, 166 /* 167 * GPIO0_7 (PWW0 OUT) 168 * DISPLAY_ONOFF (Backlight Enable at LVDS Versions) 169 */ 170 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)}, 171 /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */ 172 {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, 173 /* GPIO0_20 (DMA_INTR1) - REP-Switch */ 174 {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)}, 175 /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */ 176 {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, 177 /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */ 178 {OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) }, 179 /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */ 180 {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) }, 181 /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */ 182 {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) }, 183 #ifndef CONFIG_NAND 184 /* GPIO2_3 - NAND_OE */ 185 {OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, 186 /* GPIO2_4 - NAND_WEN */ 187 {OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, 188 /* GPIO2_5 - NAND_BE_CLE */ 189 {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)}, 190 #endif 191 {-1}, 192 }; 193 194 static struct module_pin_mux lcd_pin_mux[] = { 195 {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ 196 {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ 197 {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ 198 {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ 199 {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ 200 {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ 201 {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ 202 {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ 203 {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ 204 {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ 205 {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ 206 {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ 207 {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ 208 {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ 209 {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ 210 {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ 211 212 {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ 213 {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ 214 {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ 215 {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ 216 {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ 217 {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ 218 {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ 219 {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ 220 221 {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ 222 {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ 223 {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ 224 {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ 225 226 {-1}, 227 }; 228 229 void enable_uart0_pin_mux(void) 230 { 231 configure_module_pin_mux(uart0_pin_mux); 232 } 233 234 void enable_i2c_pin_mux(void) 235 { 236 configure_module_pin_mux(i2c0_pin_mux); 237 } 238 239 void enable_board_pin_mux(void) 240 { 241 configure_module_pin_mux(i2c0_pin_mux); 242 configure_module_pin_mux(mii1_pin_mux); 243 configure_module_pin_mux(mii2_pin_mux); 244 #ifdef CONFIG_NAND 245 configure_module_pin_mux(nand_pin_mux); 246 #elif defined(CONFIG_MMC) 247 configure_module_pin_mux(mmc1_pin_mux); 248 #endif 249 configure_module_pin_mux(spi0_pin_mux); 250 configure_module_pin_mux(lcd_pin_mux); 251 configure_module_pin_mux(uart1_pin_mux); 252 configure_module_pin_mux(gpIOs); 253 } 254