1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * board.c 4 * 5 * Board functions for B&R BRPPT1 6 * 7 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> 8 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com 9 * 10 */ 11 12 #include <common.h> 13 #include <errno.h> 14 #include <spl.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/arch/omap.h> 18 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/gpio.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/mem.h> 23 #include <asm/io.h> 24 #include <asm/emif.h> 25 #include <asm/gpio.h> 26 #include <i2c.h> 27 #include <power/tps65217.h> 28 #include "../common/bur_common.h" 29 #include <lcd.h> 30 #include <watchdog.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 /* --------------------------------------------------------------------------*/ 35 /* -- defines for GPIO -- */ 36 #define REPSWITCH (0+20) /* GPIO0_20 */ 37 38 #if defined(CONFIG_SPL_BUILD) 39 /* TODO: check ram-timing ! */ 40 static const struct ddr_data ddr3_data = { 41 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 42 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 43 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 44 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 45 }; 46 47 static const struct cmd_control ddr3_cmd_ctrl_data = { 48 .cmd0csratio = MT41K256M16HA125E_RATIO, 49 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 50 51 .cmd1csratio = MT41K256M16HA125E_RATIO, 52 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 53 54 .cmd2csratio = MT41K256M16HA125E_RATIO, 55 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 56 }; 57 58 static struct emif_regs ddr3_emif_reg_data = { 59 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 60 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 61 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 62 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 63 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 64 .zq_config = MT41K256M16HA125E_ZQ_CFG, 65 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 66 }; 67 68 static const struct ctrl_ioregs ddr3_ioregs = { 69 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 70 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 71 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 72 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 73 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 74 }; 75 76 #ifdef CONFIG_SPL_OS_BOOT 77 /* 78 * called from spl_nand.c 79 * return 0 for loading linux, return 1 for loading u-boot 80 */ 81 int spl_start_uboot(void) 82 { 83 if (0 == gpio_get_value(REPSWITCH)) { 84 mdelay(1000); 85 printf("SPL: entering u-boot instead kernel image.\n"); 86 return 1; 87 } 88 return 0; 89 } 90 #endif /* CONFIG_SPL_OS_BOOT */ 91 92 #define OSC (V_OSCK/1000000) 93 static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; 94 95 void am33xx_spl_board_init(void) 96 { 97 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; 98 /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/ 99 struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; 100 101 /* 102 * in TRM they write a reset value of 1 (=CLK_M_OSC) for the 103 * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set 104 * the source of timer6 clk to CLK_M_OSC 105 */ 106 writel(0x01, &cmdpll->clktimer6clk); 107 108 /* enable additional clocks of modules which are accessed later */ 109 u32 *const clk_domains[] = { 110 &cmper->lcdcclkstctrl, 111 0 112 }; 113 114 u32 *const clk_modules_tsspecific[] = { 115 &cmper->lcdclkctrl, 116 &cmper->timer5clkctrl, 117 &cmper->timer6clkctrl, 118 0 119 }; 120 do_enable_clocks(clk_domains, clk_modules_tsspecific, 1); 121 122 /* setup I2C */ 123 enable_i2c_pin_mux(); 124 i2c_set_bus_num(0); 125 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 126 pmicsetup(0); 127 128 gpio_direction_output(64+29, 1); /* switch NAND_RnB to GPMC_WAIT1 */ 129 gpio_direction_output(64+28, 1); /* switch MII2_CRS to GPMC_WAIT0 */ 130 } 131 132 const struct dpll_params *get_dpll_ddr_params(void) 133 { 134 return &dpll_ddr3; 135 } 136 137 void sdram_init(void) 138 { 139 config_ddr(400, &ddr3_ioregs, 140 &ddr3_data, 141 &ddr3_cmd_ctrl_data, 142 &ddr3_emif_reg_data, 0); 143 } 144 #endif /* CONFIG_SPL_BUILD */ 145 146 /* Basic board specific setup. Pinmux has been handled already. */ 147 int board_init(void) 148 { 149 #if defined(CONFIG_HW_WATCHDOG) 150 hw_watchdog_init(); 151 #endif 152 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 153 #ifdef CONFIG_NAND 154 gpmc_init(); 155 #endif 156 return 0; 157 } 158 159 #ifdef CONFIG_BOARD_LATE_INIT 160 int board_late_init(void) 161 { 162 if (0 == gpio_get_value(REPSWITCH)) { 163 lcd_position_cursor(1, 8); 164 lcd_puts( 165 "switching to network-console ... "); 166 env_set("bootcmd", "run netconsole"); 167 } 168 return 0; 169 } 170 #endif /* CONFIG_BOARD_LATE_INIT */ 171