1 /* 2 * board.c 3 * 4 * Board functions for B&R BRPPT1 5 * 6 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> 7 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 * 11 */ 12 13 #include <common.h> 14 #include <errno.h> 15 #include <spl.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/omap.h> 19 #include <asm/arch/ddr_defs.h> 20 #include <asm/arch/clock.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/sys_proto.h> 23 #include <asm/arch/mem.h> 24 #include <asm/io.h> 25 #include <asm/emif.h> 26 #include <asm/gpio.h> 27 #include <i2c.h> 28 #include <power/tps65217.h> 29 #include "../common/bur_common.h" 30 #include <lcd.h> 31 #include <watchdog.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 /* --------------------------------------------------------------------------*/ 36 /* -- defines for GPIO -- */ 37 #define REPSWITCH (0+20) /* GPIO0_20 */ 38 39 #if defined(CONFIG_SPL_BUILD) 40 /* TODO: check ram-timing ! */ 41 static const struct ddr_data ddr3_data = { 42 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 43 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 44 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 45 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 46 }; 47 48 static const struct cmd_control ddr3_cmd_ctrl_data = { 49 .cmd0csratio = MT41K256M16HA125E_RATIO, 50 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 51 52 .cmd1csratio = MT41K256M16HA125E_RATIO, 53 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 54 55 .cmd2csratio = MT41K256M16HA125E_RATIO, 56 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 57 }; 58 59 static struct emif_regs ddr3_emif_reg_data = { 60 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 61 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 62 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 63 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 64 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 65 .zq_config = MT41K256M16HA125E_ZQ_CFG, 66 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 67 }; 68 69 static const struct ctrl_ioregs ddr3_ioregs = { 70 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 71 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 72 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 73 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 74 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 75 }; 76 77 #ifdef CONFIG_SPL_OS_BOOT 78 /* 79 * called from spl_nand.c 80 * return 0 for loading linux, return 1 for loading u-boot 81 */ 82 int spl_start_uboot(void) 83 { 84 if (0 == gpio_get_value(REPSWITCH)) { 85 mdelay(1000); 86 printf("SPL: entering u-boot instead kernel image.\n"); 87 return 1; 88 } 89 return 0; 90 } 91 #endif /* CONFIG_SPL_OS_BOOT */ 92 93 #define OSC (V_OSCK/1000000) 94 static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; 95 96 void am33xx_spl_board_init(void) 97 { 98 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; 99 /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/ 100 struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; 101 102 /* 103 * in TRM they write a reset value of 1 (=CLK_M_OSC) for the 104 * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set 105 * the source of timer6 clk to CLK_M_OSC 106 */ 107 writel(0x01, &cmdpll->clktimer6clk); 108 109 /* enable additional clocks of modules which are accessed later */ 110 u32 *const clk_domains[] = { 111 &cmper->lcdcclkstctrl, 112 0 113 }; 114 115 u32 *const clk_modules_tsspecific[] = { 116 &cmper->lcdclkctrl, 117 &cmper->timer5clkctrl, 118 &cmper->timer6clkctrl, 119 0 120 }; 121 do_enable_clocks(clk_domains, clk_modules_tsspecific, 1); 122 123 /* setup LCD-Pixel Clock */ 124 writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */ 125 126 /* setup I2C */ 127 enable_i2c_pin_mux(); 128 i2c_set_bus_num(0); 129 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 130 pmicsetup(0); 131 132 gpio_direction_output(64+29, 1); /* switch NAND_RnB to GPMC_WAIT1 */ 133 gpio_direction_output(64+28, 1); /* switch MII2_CRS to GPMC_WAIT0 */ 134 } 135 136 const struct dpll_params *get_dpll_ddr_params(void) 137 { 138 return &dpll_ddr3; 139 } 140 141 void sdram_init(void) 142 { 143 config_ddr(400, &ddr3_ioregs, 144 &ddr3_data, 145 &ddr3_cmd_ctrl_data, 146 &ddr3_emif_reg_data, 0); 147 } 148 #endif /* CONFIG_SPL_BUILD */ 149 150 /* Basic board specific setup. Pinmux has been handled already. */ 151 int board_init(void) 152 { 153 #if defined(CONFIG_HW_WATCHDOG) 154 hw_watchdog_init(); 155 #endif 156 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 157 #ifdef CONFIG_NAND 158 gpmc_init(); 159 #endif 160 return 0; 161 } 162 163 #ifdef CONFIG_BOARD_LATE_INIT 164 int board_late_init(void) 165 { 166 if (0 == gpio_get_value(REPSWITCH)) { 167 lcd_position_cursor(1, 8); 168 lcd_puts( 169 "switching to network-console ... "); 170 setenv("bootcmd", "run netconsole"); 171 } 172 return 0; 173 } 174 #endif /* CONFIG_BOARD_LATE_INIT */ 175