1 /* 2 * Copyright 2013-2015 Arcturus Networks, Inc. 3 * http://www.arcturusnetworks.com/products/ucp1020/ 4 * based on board/freescale/p1_p2_rdb_pc/spl.c 5 * original copyright follows: 6 * Copyright 2013 Freescale Semiconductor, Inc. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <console.h> 13 #include <environment.h> 14 #include <ns16550.h> 15 #include <malloc.h> 16 #include <mmc.h> 17 #include <nand.h> 18 #include <i2c.h> 19 #include <fsl_esdhc.h> 20 #include <spi_flash.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 static const u32 sysclk_tbl[] = { 25 66666000, 7499900, 83332500, 8999900, 26 99999000, 11111000, 12499800, 13333200 27 }; 28 29 phys_size_t get_effective_memsize(void) 30 { 31 return CONFIG_SYS_L2_SIZE; 32 } 33 34 void board_init_f(ulong bootflag) 35 { 36 u32 plat_ratio, bus_clk; 37 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 38 39 console_init_f(); 40 41 /* Set pmuxcr to allow both i2c1 and i2c2 */ 42 setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); 43 setbits_be32(&gur->pmuxcr, 44 in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); 45 46 /* Read back the register to synchronize the write. */ 47 in_be32(&gur->pmuxcr); 48 49 #ifdef CONFIG_SPL_SPI_BOOT 50 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); 51 #endif 52 53 /* initialize selected port with appropriate baud rate */ 54 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; 55 plat_ratio >>= 1; 56 bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; 57 gd->bus_clk = bus_clk; 58 59 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 60 bus_clk / 16 / CONFIG_BAUDRATE); 61 #ifdef CONFIG_SPL_MMC_BOOT 62 puts("\nSD boot...\n"); 63 #elif defined(CONFIG_SPL_SPI_BOOT) 64 puts("\nSPI Flash boot...\n"); 65 #endif 66 67 /* copy code to RAM and jump to it - this should not return */ 68 /* NOTE - code has to be copied out of NAND buffer before 69 * other blocks can be read. 70 */ 71 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); 72 } 73 74 void board_init_r(gd_t *gd, ulong dest_addr) 75 { 76 /* Pointer is writable since we allocated a register for it */ 77 gd = (gd_t *)CONFIG_SPL_GD_ADDR; 78 bd_t *bd; 79 80 memset(gd, 0, sizeof(gd_t)); 81 bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); 82 memset(bd, 0, sizeof(bd_t)); 83 gd->bd = bd; 84 bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; 85 bd->bi_memsize = CONFIG_SYS_L2_SIZE; 86 87 arch_cpu_init(); 88 get_clocks(); 89 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, 90 CONFIG_SPL_RELOC_MALLOC_SIZE); 91 92 #ifndef CONFIG_SPL_NAND_BOOT 93 env_init(); 94 #endif 95 #ifdef CONFIG_SPL_MMC_BOOT 96 mmc_initialize(bd); 97 #endif 98 /* relocate environment function pointers etc. */ 99 #ifdef CONFIG_SPL_NAND_BOOT 100 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 101 (uchar *)CONFIG_ENV_ADDR); 102 gd->env_addr = (ulong)(CONFIG_ENV_ADDR); 103 gd->env_valid = ENV_VALID; 104 #else 105 env_relocate(); 106 #endif 107 108 #ifdef CONFIG_SYS_I2C 109 i2c_init_all(); 110 #else 111 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 112 #endif 113 114 dram_init(); 115 #ifdef CONFIG_SPL_NAND_BOOT 116 puts("Tertiary program loader running in sram..."); 117 #else 118 puts("Second program loader running in sram...\n"); 119 #endif 120 121 #ifdef CONFIG_SPL_MMC_BOOT 122 mmc_boot(); 123 #elif defined(CONFIG_SPL_NAND_BOOT) 124 nand_boot(); 125 #endif 126 } 127