1 /* 2 * Copyright 2013-2015 Arcturus Networks, Inc. 3 * http://www.arcturusnetworks.com/products/ucp1020/ 4 * based on board/freescale/p1_p2_rdb_pc/spl.c 5 * original copyright follows: 6 * Copyright 2013 Freescale Semiconductor, Inc. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <asm/mmu.h> 13 #include <asm/immap_85xx.h> 14 #include <asm/processor.h> 15 #include <fsl_ddr_sdram.h> 16 #include <fsl_ddr_dimm_params.h> 17 #include <asm/io.h> 18 #include <asm/fsl_law.h> 19 20 #ifdef CONFIG_SYS_DDR_RAW_TIMING 21 #if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1) 22 /* 23 * Micron MT41J128M16HA-15E 24 * */ 25 dimm_params_t ddr_raw_timing = { 26 .n_ranks = 1, 27 .rank_density = 536870912u, 28 .capacity = 536870912u, 29 .primary_sdram_width = 32, 30 .ec_sdram_width = 8, 31 .registered_dimm = 0, 32 .mirrored_dimm = 0, 33 .n_row_addr = 14, 34 .n_col_addr = 10, 35 .n_banks_per_sdram_device = 8, 36 .edc_config = 2, 37 .burst_lengths_bitmask = 0x0c, 38 39 .tckmin_x_ps = 1650, 40 .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */ 41 .taa_ps = 14050, 42 .twr_ps = 15000, 43 .trcd_ps = 13500, 44 .trrd_ps = 75000, 45 .trp_ps = 13500, 46 .tras_ps = 40000, 47 .trc_ps = 49500, 48 .trfc_ps = 160000, 49 .twtr_ps = 75000, 50 .trtp_ps = 75000, 51 .refresh_rate_ps = 7800000, 52 .tfaw_ps = 30000, 53 }; 54 55 #else 56 #error Missing raw timing data for this board 57 #endif 58 59 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 60 unsigned int controller_number, 61 unsigned int dimm_number) 62 { 63 const char dimm_model[] = "Fixed DDR on board"; 64 65 if ((controller_number == 0) && (dimm_number == 0)) { 66 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 67 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 68 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 69 } 70 71 return 0; 72 } 73 #endif /* CONFIG_SYS_DDR_RAW_TIMING */ 74 75 #ifdef CONFIG_SYS_DDR_CS0_BNDS 76 /* Fixed sdram init -- doesn't use serial presence detect. */ 77 phys_size_t fixed_sdram(void) 78 { 79 sys_info_t sysinfo; 80 char buf[32]; 81 size_t ddr_size; 82 fsl_ddr_cfg_regs_t ddr_cfg_regs = { 83 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, 84 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, 85 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, 86 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1 87 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, 88 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, 89 .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, 90 #endif 91 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, 92 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, 93 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, 94 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, 95 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, 96 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, 97 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, 98 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, 99 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, 100 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, 101 .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT, 102 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, 103 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, 104 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, 105 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, 106 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 107 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, 108 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, 109 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, 110 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, 111 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 112 }; 113 114 get_sys_info(&sysinfo); 115 printf("Configuring DDR for %s MT/s data rate\n", 116 strmhz(buf, sysinfo.freq_ddrbus)); 117 118 ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 119 120 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); 121 122 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, 123 ddr_size, LAW_TRGT_IF_DDR_1) < 0) { 124 printf("ERROR setting Local Access Windows for DDR\n"); 125 return 0; 126 }; 127 128 return ddr_size; 129 } 130 #endif 131 132 void fsl_ddr_board_options(memctl_options_t *popts, 133 dimm_params_t *pdimm, 134 unsigned int ctrl_num) 135 { 136 int i; 137 138 popts->clk_adjust = 6; 139 popts->cpo_override = 0x1f; 140 popts->write_data_delay = 2; 141 popts->half_strength_driver_enable = 1; 142 /* Write leveling override */ 143 popts->wrlvl_en = 1; 144 popts->wrlvl_override = 1; 145 popts->wrlvl_sample = 0xf; 146 popts->wrlvl_start = 0x8; 147 popts->trwt_override = 1; 148 popts->trwt = 0; 149 150 if (pdimm->primary_sdram_width == 64) 151 popts->data_bus_width = 0; 152 else if (pdimm->primary_sdram_width == 32) 153 popts->data_bus_width = 1; 154 else 155 printf("Error in DDR bus width configuration!\n"); 156 157 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 158 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; 159 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; 160 } 161 } 162